forked from luck/tmp_suning_uos_patched
61f9c58da5
Replace the current sysctl-based suspend interface with a new sysfs-
based one which also uses the Linux-2.6 suspend model.
To configure wakeup sources, a subtree for the demoboards is created
under /sys/power/db1x:
sys/
`-- power
`-- db1x
|-- gpio0
|-- gpio1
|-- gpio2
|-- gpio3
|-- gpio4
|-- gpio5
|-- gpio6
|-- gpio7
|-- timer
|-- timer_timeout
|-- wakemsk
`-- wakesrc
The nodes 'gpio[0-7]' and 'timer' configure the GPIO0..7 and M2
bits of the SYS_WAKEMSK (wakeup source enable) register. Writing '1'
enables a wakesource, 0 disables it.
The 'timer_timeout' node holds the timeout in seconds after which the
TOYMATCH2 event should wake the system.
The 'wakesrc' node holds the SYS_WAKESRC register after wakeup (in hex),
the 'wakemsk' node can be used to get/set the wakeup mask directly.
For example, to have the timer wake the system after 10 seconds of sleep,
the following must be done in userspace:
echo 10 > /sys/power/db1x/timer_timeout
echo 1 > /sys/power/db1x/timer
echo mem > /sys/power/sleep
This patch also removes the homebrew CPU frequency switching code. I don't
understand how it could have ever worked reliably; it does not communicate
the clock changes to peripheral devices other than uarts.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
create mode 100644 arch/mips/alchemy/devboards/pm.c
218 lines
7.4 KiB
C
218 lines
7.4 KiB
C
/*
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* BRIEF MODULE DESCRIPTION
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* Au1xx0 Power Management routines.
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*
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* Some of the routines are right out of init/main.c, whose
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* copyrights apply here.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/sysctl.h>
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#include <linux/jiffies.h>
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#include <asm/uaccess.h>
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#include <asm/mach-au1x00/au1000.h>
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#endif
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#ifdef CONFIG_PM
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/*
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* We need to save/restore a bunch of core registers that are
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* either volatile or reset to some state across a processor sleep.
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* If reading a register doesn't provide a proper result for a
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* later restore, we have to provide a function for loading that
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* register and save a copy.
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*
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* We only have to save/restore registers that aren't otherwise
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* done as part of a driver pm_* function.
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*/
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static unsigned int sleep_uart0_inten;
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static unsigned int sleep_uart0_fifoctl;
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static unsigned int sleep_uart0_linectl;
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static unsigned int sleep_uart0_clkdiv;
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static unsigned int sleep_uart0_enable;
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static unsigned int sleep_usb[2];
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static unsigned int sleep_sys_clocks[5];
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static unsigned int sleep_sys_pinfunc;
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static unsigned int sleep_static_memctlr[4][3];
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static void save_core_regs(void)
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{
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extern void save_au1xxx_intctl(void);
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extern void pm_eth0_shutdown(void);
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/*
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* Do the serial ports.....these really should be a pm_*
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* registered function by the driver......but of course the
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* standard serial driver doesn't understand our Au1xxx
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* unique registers.
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*/
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sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
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sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
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sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
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sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
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sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
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au_sync();
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#ifndef CONFIG_SOC_AU1200
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/* Shutdown USB host/device. */
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sleep_usb[0] = au_readl(USB_HOST_CONFIG);
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/* There appears to be some undocumented reset register.... */
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au_writel(0, 0xb0100004);
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au_sync();
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au_writel(0, USB_HOST_CONFIG);
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au_sync();
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sleep_usb[1] = au_readl(USBD_ENABLE);
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au_writel(0, USBD_ENABLE);
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au_sync();
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#else /* AU1200 */
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/* enable access to OTG mmio so we can save OTG CAP/MUX.
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* FIXME: write an OTG driver and move this stuff there!
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*/
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au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
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au_sync();
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sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
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sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
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#endif
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/* Save interrupt controller state. */
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save_au1xxx_intctl();
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/* Clocks and PLLs. */
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sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
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sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
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sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
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sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
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sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
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/* pin mux config */
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sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
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/* Save the static memory controller configuration. */
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sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
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sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
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sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
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sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
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sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
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sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
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sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
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sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
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sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
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sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
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sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
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sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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au1xxx_dbdma_suspend();
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#endif
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}
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static void restore_core_regs(void)
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{
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/* restore clock configuration. Writing CPUPLL last will
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* stall a bit and stabilize other clocks (unless this is
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* one of those Au1000 with a write-only PLL, where we dont
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* have a valid value)
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*/
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au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
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au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
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au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
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au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
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if (!au1xxx_cpu_has_pll_wo())
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au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
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au_sync();
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au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
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au_sync();
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#ifndef CONFIG_SOC_AU1200
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au_writel(sleep_usb[0], USB_HOST_CONFIG);
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au_writel(sleep_usb[1], USBD_ENABLE);
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au_sync();
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#else
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/* enable accces to OTG memory */
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au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
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au_sync();
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/* restore OTG caps and port mux. */
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au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
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au_sync();
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au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
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au_sync();
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#endif
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/* Restore the static memory controller configuration. */
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au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
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au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
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au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
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au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
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au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
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au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
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au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
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au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
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au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
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au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
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au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
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au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
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/*
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* Enable the UART if it was enabled before sleep.
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* I guess I should define module control bits........
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*/
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if (sleep_uart0_enable & 0x02) {
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au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
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au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
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au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
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au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
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au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
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au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
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au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
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}
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restore_au1xxx_intctl();
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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au1xxx_dbdma_resume();
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#endif
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}
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void au_sleep(void)
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{
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save_core_regs();
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au1xxx_save_and_sleep();
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restore_core_regs();
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}
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#endif /* CONFIG_PM */
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