forked from luck/tmp_suning_uos_patched
fc24d75a7f
While in the native case entry into the kernel happens on the trampoline
stack, PV Xen kernels get entered with the current thread stack right
away. Hence source and destination stacks are identical in that case,
and special care is needed.
Other than in sync_regs() the copying done on the INT80 path isn't
NMI / #MC safe, as either of these events occurring in the middle of the
stack copying would clobber data on the (source) stack.
There is similar code in interrupt_entry() and nmi(), but there is no fixup
required because those code paths are unreachable in XEN PV guests.
[ tglx: Sanitized subject, changelog, Fixes tag and stable mail address. Sigh ]
Fixes: 7f2590a110 ("x86/entry/64: Use a per-CPU trampoline stack for IDT entries")
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Juergen Gross <jgross@suse.com>
Acked-by: Andy Lutomirski <luto@kernel.org>
Cc: Peter Anvin <hpa@zytor.com>
Cc: xen-devel@lists.xenproject.org>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/5C3E1128020000780020DFAD@prv1-mh.provo.novell.com
420 lines
14 KiB
ArmAsm
420 lines
14 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Compatibility mode system call entry point for x86-64.
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*
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* Copyright 2000-2002 Andi Kleen, SuSE Labs.
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*/
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#include "calling.h"
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#include <asm/asm-offsets.h>
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#include <asm/current.h>
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#include <asm/errno.h>
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#include <asm/ia32_unistd.h>
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#include <asm/thread_info.h>
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#include <asm/segment.h>
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#include <asm/irqflags.h>
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#include <asm/asm.h>
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#include <asm/smap.h>
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#include <linux/linkage.h>
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#include <linux/err.h>
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.section .entry.text, "ax"
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/*
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* 32-bit SYSENTER entry.
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*
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* 32-bit system calls through the vDSO's __kernel_vsyscall enter here
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* on 64-bit kernels running on Intel CPUs.
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*
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* The SYSENTER instruction, in principle, should *only* occur in the
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* vDSO. In practice, a small number of Android devices were shipped
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* with a copy of Bionic that inlined a SYSENTER instruction. This
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* never happened in any of Google's Bionic versions -- it only happened
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* in a narrow range of Intel-provided versions.
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*
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* SYSENTER loads SS, RSP, CS, and RIP from previously programmed MSRs.
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* IF and VM in RFLAGS are cleared (IOW: interrupts are off).
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* SYSENTER does not save anything on the stack,
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* and does not save old RIP (!!!), RSP, or RFLAGS.
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*
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* Arguments:
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* eax system call number
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* ebx arg1
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* ecx arg2
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* edx arg3
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* esi arg4
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* edi arg5
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* ebp user stack
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* 0(%ebp) arg6
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*/
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ENTRY(entry_SYSENTER_compat)
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/* Interrupts are off on entry. */
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SWAPGS
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/* We are about to clobber %rsp anyway, clobbering here is OK */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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/*
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* User tracing code (ptrace or signal handlers) might assume that
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* the saved RAX contains a 32-bit number when we're invoking a 32-bit
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* syscall. Just in case the high bits are nonzero, zero-extend
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* the syscall number. (This could almost certainly be deleted
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* with no ill effects.)
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*/
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movl %eax, %eax
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/* Construct struct pt_regs on stack */
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pushq $__USER32_DS /* pt_regs->ss */
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pushq %rbp /* pt_regs->sp (stashed in bp) */
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/*
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* Push flags. This is nasty. First, interrupts are currently
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* off, but we need pt_regs->flags to have IF set. Second, even
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* if TF was set when SYSENTER started, it's clear by now. We fix
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* that later using TIF_SINGLESTEP.
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*/
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pushfq /* pt_regs->flags (except IF = 0) */
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orl $X86_EFLAGS_IF, (%rsp) /* Fix saved flags */
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pushq $__USER32_CS /* pt_regs->cs */
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pushq $0 /* pt_regs->ip = 0 (placeholder) */
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pushq %rax /* pt_regs->orig_ax */
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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pushq %rdx /* pt_regs->dx */
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pushq %rcx /* pt_regs->cx */
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pushq $-ENOSYS /* pt_regs->ax */
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pushq $0 /* pt_regs->r8 = 0 */
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xorl %r8d, %r8d /* nospec r8 */
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pushq $0 /* pt_regs->r9 = 0 */
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xorl %r9d, %r9d /* nospec r9 */
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pushq $0 /* pt_regs->r10 = 0 */
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xorl %r10d, %r10d /* nospec r10 */
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pushq $0 /* pt_regs->r11 = 0 */
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xorl %r11d, %r11d /* nospec r11 */
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pushq %rbx /* pt_regs->rbx */
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xorl %ebx, %ebx /* nospec rbx */
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pushq %rbp /* pt_regs->rbp (will be overwritten) */
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xorl %ebp, %ebp /* nospec rbp */
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pushq $0 /* pt_regs->r12 = 0 */
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xorl %r12d, %r12d /* nospec r12 */
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pushq $0 /* pt_regs->r13 = 0 */
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xorl %r13d, %r13d /* nospec r13 */
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pushq $0 /* pt_regs->r14 = 0 */
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xorl %r14d, %r14d /* nospec r14 */
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pushq $0 /* pt_regs->r15 = 0 */
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xorl %r15d, %r15d /* nospec r15 */
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cld
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/*
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* SYSENTER doesn't filter flags, so we need to clear NT and AC
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* ourselves. To save a few cycles, we can check whether
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* either was set instead of doing an unconditional popfq.
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* This needs to happen before enabling interrupts so that
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* we don't get preempted with NT set.
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*
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* If TF is set, we will single-step all the way to here -- do_debug
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* will ignore all the traps. (Yes, this is slow, but so is
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* single-stepping in general. This allows us to avoid having
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* a more complicated code to handle the case where a user program
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* forces us to single-step through the SYSENTER entry code.)
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*
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* NB.: .Lsysenter_fix_flags is a label with the code under it moved
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* out-of-line as an optimization: NT is unlikely to be set in the
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* majority of the cases and instead of polluting the I$ unnecessarily,
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* we're keeping that code behind a branch which will predict as
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* not-taken and therefore its instructions won't be fetched.
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*/
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testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, EFLAGS(%rsp)
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jnz .Lsysenter_fix_flags
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.Lsysenter_flags_fixed:
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/*
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* User mode is traced as though IRQs are on, and SYSENTER
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* turned them off.
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*/
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TRACE_IRQS_OFF
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movq %rsp, %rdi
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call do_fast_syscall_32
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/* XEN PV guests always use IRET path */
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ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \
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"jmp .Lsyscall_32_done", X86_FEATURE_XENPV
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jmp sysret32_from_system_call
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.Lsysenter_fix_flags:
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pushq $X86_EFLAGS_FIXED
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popfq
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jmp .Lsysenter_flags_fixed
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GLOBAL(__end_entry_SYSENTER_compat)
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ENDPROC(entry_SYSENTER_compat)
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/*
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* 32-bit SYSCALL entry.
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*
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* 32-bit system calls through the vDSO's __kernel_vsyscall enter here
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* on 64-bit kernels running on AMD CPUs.
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*
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* The SYSCALL instruction, in principle, should *only* occur in the
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* vDSO. In practice, it appears that this really is the case.
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* As evidence:
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*
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* - The calling convention for SYSCALL has changed several times without
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* anyone noticing.
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*
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* - Prior to the in-kernel X86_BUG_SYSRET_SS_ATTRS fixup, anything
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* user task that did SYSCALL without immediately reloading SS
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* would randomly crash.
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*
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* - Most programmers do not directly target AMD CPUs, and the 32-bit
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* SYSCALL instruction does not exist on Intel CPUs. Even on AMD
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* CPUs, Linux disables the SYSCALL instruction on 32-bit kernels
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* because the SYSCALL instruction in legacy/native 32-bit mode (as
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* opposed to compat mode) is sufficiently poorly designed as to be
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* essentially unusable.
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*
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* 32-bit SYSCALL saves RIP to RCX, clears RFLAGS.RF, then saves
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* RFLAGS to R11, then loads new SS, CS, and RIP from previously
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* programmed MSRs. RFLAGS gets masked by a value from another MSR
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* (so CLD and CLAC are not needed). SYSCALL does not save anything on
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* the stack and does not change RSP.
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*
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* Note: RFLAGS saving+masking-with-MSR happens only in Long mode
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* (in legacy 32-bit mode, IF, RF and VM bits are cleared and that's it).
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* Don't get confused: RFLAGS saving+masking depends on Long Mode Active bit
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* (EFER.LMA=1), NOT on bitness of userspace where SYSCALL executes
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* or target CS descriptor's L bit (SYSCALL does not read segment descriptors).
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*
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* Arguments:
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* eax system call number
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* ecx return address
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* ebx arg1
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* ebp arg2 (note: not saved in the stack frame, should not be touched)
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* edx arg3
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* esi arg4
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* edi arg5
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* esp user stack
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* 0(%esp) arg6
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*/
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ENTRY(entry_SYSCALL_compat)
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/* Interrupts are off on entry. */
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swapgs
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/* Stash user ESP */
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movl %esp, %r8d
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/* Use %rsp as scratch reg. User ESP is stashed in r8 */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp
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/* Switch to the kernel stack */
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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/* Construct struct pt_regs on stack */
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pushq $__USER32_DS /* pt_regs->ss */
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pushq %r8 /* pt_regs->sp */
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pushq %r11 /* pt_regs->flags */
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pushq $__USER32_CS /* pt_regs->cs */
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pushq %rcx /* pt_regs->ip */
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GLOBAL(entry_SYSCALL_compat_after_hwframe)
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movl %eax, %eax /* discard orig_ax high bits */
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pushq %rax /* pt_regs->orig_ax */
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pushq %rdi /* pt_regs->di */
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pushq %rsi /* pt_regs->si */
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xorl %esi, %esi /* nospec si */
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pushq %rdx /* pt_regs->dx */
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xorl %edx, %edx /* nospec dx */
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pushq %rbp /* pt_regs->cx (stashed in bp) */
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xorl %ecx, %ecx /* nospec cx */
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pushq $-ENOSYS /* pt_regs->ax */
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pushq $0 /* pt_regs->r8 = 0 */
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xorl %r8d, %r8d /* nospec r8 */
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pushq $0 /* pt_regs->r9 = 0 */
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xorl %r9d, %r9d /* nospec r9 */
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pushq $0 /* pt_regs->r10 = 0 */
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xorl %r10d, %r10d /* nospec r10 */
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pushq $0 /* pt_regs->r11 = 0 */
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xorl %r11d, %r11d /* nospec r11 */
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pushq %rbx /* pt_regs->rbx */
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xorl %ebx, %ebx /* nospec rbx */
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pushq %rbp /* pt_regs->rbp (will be overwritten) */
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xorl %ebp, %ebp /* nospec rbp */
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pushq $0 /* pt_regs->r12 = 0 */
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xorl %r12d, %r12d /* nospec r12 */
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pushq $0 /* pt_regs->r13 = 0 */
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xorl %r13d, %r13d /* nospec r13 */
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pushq $0 /* pt_regs->r14 = 0 */
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xorl %r14d, %r14d /* nospec r14 */
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pushq $0 /* pt_regs->r15 = 0 */
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xorl %r15d, %r15d /* nospec r15 */
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/*
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* User mode is traced as though IRQs are on, and SYSENTER
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* turned them off.
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*/
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TRACE_IRQS_OFF
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movq %rsp, %rdi
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call do_fast_syscall_32
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/* XEN PV guests always use IRET path */
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ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \
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"jmp .Lsyscall_32_done", X86_FEATURE_XENPV
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/* Opportunistic SYSRET */
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sysret32_from_system_call:
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/*
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* We are not going to return to userspace from the trampoline
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* stack. So let's erase the thread stack right now.
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*/
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STACKLEAK_ERASE
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TRACE_IRQS_ON /* User mode traces as IRQs on. */
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movq RBX(%rsp), %rbx /* pt_regs->rbx */
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movq RBP(%rsp), %rbp /* pt_regs->rbp */
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movq EFLAGS(%rsp), %r11 /* pt_regs->flags (in r11) */
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movq RIP(%rsp), %rcx /* pt_regs->ip (in rcx) */
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addq $RAX, %rsp /* Skip r8-r15 */
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popq %rax /* pt_regs->rax */
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popq %rdx /* Skip pt_regs->cx */
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popq %rdx /* pt_regs->dx */
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popq %rsi /* pt_regs->si */
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popq %rdi /* pt_regs->di */
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/*
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* USERGS_SYSRET32 does:
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* GSBASE = user's GS base
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* EIP = ECX
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* RFLAGS = R11
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* CS = __USER32_CS
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* SS = __USER_DS
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*
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* ECX will not match pt_regs->cx, but we're returning to a vDSO
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* trampoline that will fix up RCX, so this is okay.
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*
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* R12-R15 are callee-saved, so they contain whatever was in them
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* when the system call started, which is already known to user
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* code. We zero R8-R10 to avoid info leaks.
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*/
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movq RSP-ORIG_RAX(%rsp), %rsp
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/*
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* The original userspace %rsp (RSP-ORIG_RAX(%rsp)) is stored
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* on the process stack which is not mapped to userspace and
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* not readable after we SWITCH_TO_USER_CR3. Delay the CR3
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* switch until after after the last reference to the process
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* stack.
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*
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* %r8/%r9 are zeroed before the sysret, thus safe to clobber.
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*/
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SWITCH_TO_USER_CR3_NOSTACK scratch_reg=%r8 scratch_reg2=%r9
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xorl %r8d, %r8d
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xorl %r9d, %r9d
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xorl %r10d, %r10d
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swapgs
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sysretl
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END(entry_SYSCALL_compat)
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/*
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* 32-bit legacy system call entry.
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*
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* 32-bit x86 Linux system calls traditionally used the INT $0x80
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* instruction. INT $0x80 lands here.
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*
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* This entry point can be used by 32-bit and 64-bit programs to perform
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* 32-bit system calls. Instances of INT $0x80 can be found inline in
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* various programs and libraries. It is also used by the vDSO's
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* __kernel_vsyscall fallback for hardware that doesn't support a faster
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* entry method. Restarted 32-bit system calls also fall back to INT
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* $0x80 regardless of what instruction was originally used to do the
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* system call.
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*
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* This is considered a slow path. It is not used by most libc
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* implementations on modern hardware except during process startup.
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*
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* Arguments:
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* eax system call number
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* ebx arg1
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* ecx arg2
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* edx arg3
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* esi arg4
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* edi arg5
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* ebp arg6
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*/
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ENTRY(entry_INT80_compat)
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/*
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* Interrupts are off on entry.
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*/
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ASM_CLAC /* Do this early to minimize exposure */
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SWAPGS
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/*
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* User tracing code (ptrace or signal handlers) might assume that
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* the saved RAX contains a 32-bit number when we're invoking a 32-bit
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* syscall. Just in case the high bits are nonzero, zero-extend
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* the syscall number. (This could almost certainly be deleted
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* with no ill effects.)
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*/
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movl %eax, %eax
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/* switch to thread stack expects orig_ax and rdi to be pushed */
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pushq %rax /* pt_regs->orig_ax */
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pushq %rdi /* pt_regs->di */
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/* Need to switch before accessing the thread stack. */
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SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi
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/* In the Xen PV case we already run on the thread stack. */
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ALTERNATIVE "movq %rsp, %rdi", "jmp .Lint80_keep_stack", X86_FEATURE_XENPV
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movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp
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pushq 6*8(%rdi) /* regs->ss */
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pushq 5*8(%rdi) /* regs->rsp */
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pushq 4*8(%rdi) /* regs->eflags */
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pushq 3*8(%rdi) /* regs->cs */
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pushq 2*8(%rdi) /* regs->ip */
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pushq 1*8(%rdi) /* regs->orig_ax */
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pushq (%rdi) /* pt_regs->di */
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.Lint80_keep_stack:
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pushq %rsi /* pt_regs->si */
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xorl %esi, %esi /* nospec si */
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pushq %rdx /* pt_regs->dx */
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xorl %edx, %edx /* nospec dx */
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pushq %rcx /* pt_regs->cx */
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xorl %ecx, %ecx /* nospec cx */
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pushq $-ENOSYS /* pt_regs->ax */
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pushq %r8 /* pt_regs->r8 */
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xorl %r8d, %r8d /* nospec r8 */
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pushq %r9 /* pt_regs->r9 */
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xorl %r9d, %r9d /* nospec r9 */
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pushq %r10 /* pt_regs->r10*/
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xorl %r10d, %r10d /* nospec r10 */
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pushq %r11 /* pt_regs->r11 */
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xorl %r11d, %r11d /* nospec r11 */
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pushq %rbx /* pt_regs->rbx */
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xorl %ebx, %ebx /* nospec rbx */
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pushq %rbp /* pt_regs->rbp */
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xorl %ebp, %ebp /* nospec rbp */
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pushq %r12 /* pt_regs->r12 */
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xorl %r12d, %r12d /* nospec r12 */
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pushq %r13 /* pt_regs->r13 */
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xorl %r13d, %r13d /* nospec r13 */
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pushq %r14 /* pt_regs->r14 */
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xorl %r14d, %r14d /* nospec r14 */
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pushq %r15 /* pt_regs->r15 */
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xorl %r15d, %r15d /* nospec r15 */
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cld
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/*
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* User mode is traced as though IRQs are on, and the interrupt
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* gate turned them off.
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*/
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TRACE_IRQS_OFF
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movq %rsp, %rdi
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call do_int80_syscall_32
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.Lsyscall_32_done:
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/* Go back to user mode. */
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TRACE_IRQS_ON
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jmp swapgs_restore_regs_and_return_to_usermode
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END(entry_INT80_compat)
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