forked from luck/tmp_suning_uos_patched
3dd9d51484
Appended patch adds the support for Intel dual-core detection and displaying
the core related information in /proc/cpuinfo.
It adds two new fields "core id" and "cpu cores" to x86 /proc/cpuinfo and the
"core id" field for x86_64("cpu cores" field is already present in x86_64).
Number of processor cores in a die is detected using cpuid(4) and this is
documented in IA-32 Intel Architecture Software Developer's Manual (vol 2a)
(http://developer.intel.com/design/pentium4/manuals/index_new.htm#sdm_vol2a)
This patch also adds cpu_core_map similar to cpu_sibling_map.
Slightly hacked by AK.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
692 lines
18 KiB
C
692 lines
18 KiB
C
/*
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* include/asm-i386/processor.h
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*
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* Copyright (C) 1994 Linus Torvalds
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*/
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#ifndef __ASM_I386_PROCESSOR_H
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#define __ASM_I386_PROCESSOR_H
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#include <asm/vm86.h>
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#include <asm/math_emu.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/sigcontext.h>
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#include <asm/cpufeature.h>
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#include <asm/msr.h>
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#include <asm/system.h>
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#include <linux/cache.h>
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <asm/percpu.h>
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/* flag for disabling the tsc */
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extern int tsc_disable;
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struct desc_struct {
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unsigned long a,b;
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};
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#define desc_empty(desc) \
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(!((desc)->a + (desc)->b))
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#define desc_equal(desc1, desc2) \
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(((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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* Members of this structure are referenced in head.S, so think twice
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* before touching them. [mj]
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*/
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struct cpuinfo_x86 {
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__u8 x86; /* CPU family */
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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__u8 x86_mask;
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char wp_works_ok; /* It doesn't on 386's */
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char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
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char hard_math;
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char rfu;
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int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
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unsigned long x86_capability[NCAPINTS];
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char x86_vendor_id[16];
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char x86_model_id[64];
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int x86_cache_size; /* in KB - valid for CPUS which support this
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call */
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int x86_cache_alignment; /* In bytes */
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int fdiv_bug;
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int f00f_bug;
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int coma_bug;
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unsigned long loops_per_jiffy;
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unsigned char x86_num_cores;
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} __attribute__((__aligned__(SMP_CACHE_BYTES)));
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_NEXGEN 4
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_RISE 6
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_UNKNOWN 0xff
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/*
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* capabilities of CPUs
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*/
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extern struct cpuinfo_x86 boot_cpu_data;
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct tss_struct doublefault_tss;
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DECLARE_PER_CPU(struct tss_struct, init_tss);
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#ifdef CONFIG_SMP
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extern struct cpuinfo_x86 cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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#else
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#define cpu_data (&boot_cpu_data)
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#define current_cpu_data boot_cpu_data
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#endif
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extern int phys_proc_id[NR_CPUS];
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extern int cpu_core_id[NR_CPUS];
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extern char ignore_fpu_irq;
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extern void identify_cpu(struct cpuinfo_x86 *);
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extern void print_cpu_info(struct cpuinfo_x86 *);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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#ifdef CONFIG_X86_HT
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extern void detect_ht(struct cpuinfo_x86 *c);
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#else
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static inline void detect_ht(struct cpuinfo_x86 *c) {}
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#endif
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/*
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* EFLAGS bits
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*/
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#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
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#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
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#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
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#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
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#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
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#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
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#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
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#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
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#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
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#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
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#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
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#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
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#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
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#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
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#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
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#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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/*
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* Generic CPUID function
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* clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
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* resulting in stale register contents being returned.
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*/
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static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
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{
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__asm__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (op), "c"(0));
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}
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/* Some CPUID calls want 'count' to be placed in ecx */
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static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
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int *edx)
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{
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__asm__("cpuid"
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: "=a" (*eax),
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"=b" (*ebx),
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"=c" (*ecx),
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"=d" (*edx)
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: "0" (op), "c" (count));
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}
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/*
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* CPUID functions returning a single datum
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*/
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax;
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__asm__("cpuid"
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: "=a" (eax)
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: "0" (op)
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: "bx", "cx", "dx");
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return eax;
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}
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static inline unsigned int cpuid_ebx(unsigned int op)
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{
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unsigned int eax, ebx;
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__asm__("cpuid"
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: "=a" (eax), "=b" (ebx)
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: "0" (op)
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: "cx", "dx" );
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return ebx;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ecx;
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__asm__("cpuid"
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: "=a" (eax), "=c" (ecx)
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: "0" (op)
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: "bx", "dx" );
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, edx;
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__asm__("cpuid"
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: "=a" (eax), "=d" (edx)
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: "0" (op)
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: "bx", "cx");
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return edx;
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}
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#define load_cr3(pgdir) \
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asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
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/*
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* Intel CPU features in CR4
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*/
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#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
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#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
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#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
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#define X86_CR4_DE 0x0008 /* enable debugging extensions */
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#define X86_CR4_PSE 0x0010 /* enable page size extensions */
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#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
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#define X86_CR4_MCE 0x0040 /* Machine check enable */
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#define X86_CR4_PGE 0x0080 /* enable global pages */
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#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
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#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
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#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
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/*
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* Save the cr4 feature set we're using (ie
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* Pentium 4MB enable and PPro Global page
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* enable), so that any CPU's that boot up
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* after us can get the correct flags.
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*/
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extern unsigned long mmu_cr4_features;
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static inline void set_in_cr4 (unsigned long mask)
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{
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mmu_cr4_features |= mask;
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__asm__("movl %%cr4,%%eax\n\t"
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"orl %0,%%eax\n\t"
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"movl %%eax,%%cr4\n"
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: : "irg" (mask)
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:"ax");
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}
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static inline void clear_in_cr4 (unsigned long mask)
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{
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mmu_cr4_features &= ~mask;
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__asm__("movl %%cr4,%%eax\n\t"
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"andl %0,%%eax\n\t"
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"movl %%eax,%%cr4\n"
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: : "irg" (~mask)
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:"ax");
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}
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/*
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* NSC/Cyrix CPU configuration register indexes
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*/
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#define CX86_PCR0 0x20
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#define CX86_GCR 0xb8
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#define CX86_CCR0 0xc0
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#define CX86_CCR1 0xc1
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#define CX86_CCR2 0xc2
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#define CX86_CCR3 0xc3
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#define CX86_CCR4 0xe8
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#define CX86_CCR5 0xe9
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#define CX86_CCR6 0xea
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#define CX86_CCR7 0xeb
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#define CX86_PCR1 0xf0
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#define CX86_DIR0 0xfe
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#define CX86_DIR1 0xff
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#define CX86_ARR_BASE 0xc4
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#define CX86_RCR_BASE 0xdc
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/*
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* NSC/Cyrix CPU indexed register access macros
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*/
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#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
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#define setCx86(reg, data) do { \
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outb((reg), 0x22); \
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outb((data), 0x23); \
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} while (0)
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static inline void __monitor(const void *eax, unsigned long ecx,
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unsigned long edx)
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{
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/* "monitor %eax,%ecx,%edx;" */
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asm volatile(
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".byte 0x0f,0x01,0xc8;"
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: :"a" (eax), "c" (ecx), "d"(edx));
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}
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static inline void __mwait(unsigned long eax, unsigned long ecx)
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{
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/* "mwait %eax,%ecx;" */
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asm volatile(
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".byte 0x0f,0x01,0xc9;"
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: :"a" (eax), "c" (ecx));
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}
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/* from system description table in BIOS. Mostly for MCA use, but
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others may find it useful. */
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extern unsigned int machine_id;
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extern unsigned int machine_submodel_id;
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extern unsigned int BIOS_revision;
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extern unsigned int mca_pentium_flag;
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/* Boot loader type from the setup header */
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extern int bootloader_type;
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/*
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* User space process size: 3GB (default).
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*/
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#define TASK_SIZE (PAGE_OFFSET)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
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#define HAVE_ARCH_PICK_MMAP_LAYOUT
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/*
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* Size of io_bitmap.
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
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struct i387_fsave_struct {
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long cwd;
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long swd;
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long twd;
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long fip;
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long fcs;
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long foo;
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long fos;
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long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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long status; /* software status information */
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};
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struct i387_fxsave_struct {
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unsigned short cwd;
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unsigned short swd;
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unsigned short twd;
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unsigned short fop;
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long fip;
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long fcs;
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long foo;
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long fos;
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long mxcsr;
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long mxcsr_mask;
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long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
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long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
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long padding[56];
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} __attribute__ ((aligned (16)));
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struct i387_soft_struct {
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long cwd;
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long swd;
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long twd;
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long fip;
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long fcs;
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long foo;
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long fos;
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long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
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unsigned char ftop, changed, lookahead, no_update, rm, alimit;
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struct info *info;
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unsigned long entry_eip;
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};
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union i387_union {
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struct i387_fsave_struct fsave;
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struct i387_fxsave_struct fxsave;
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struct i387_soft_struct soft;
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};
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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struct thread_struct;
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struct tss_struct {
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unsigned short back_link,__blh;
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unsigned long esp0;
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unsigned short ss0,__ss0h;
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unsigned long esp1;
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unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
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unsigned long esp2;
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unsigned short ss2,__ss2h;
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unsigned long __cr3;
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unsigned long eip;
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unsigned long eflags;
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unsigned long eax,ecx,edx,ebx;
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unsigned long esp;
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unsigned long ebp;
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unsigned long esi;
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unsigned long edi;
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unsigned short es, __esh;
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unsigned short cs, __csh;
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unsigned short ss, __ssh;
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unsigned short ds, __dsh;
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unsigned short fs, __fsh;
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unsigned short gs, __gsh;
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unsigned short ldt, __ldth;
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unsigned short trace, io_bitmap_base;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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/*
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* Cache the current maximum and the last task that used the bitmap:
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*/
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unsigned long io_bitmap_max;
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struct thread_struct *io_bitmap_owner;
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/*
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* pads the TSS to be cacheline-aligned (size is 0x100)
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*/
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unsigned long __cacheline_filler[35];
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/*
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* .. and then another 0x100 bytes for emergency kernel stack
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*/
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unsigned long stack[64];
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} __attribute__((packed));
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#define ARCH_MIN_TASKALIGN 16
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struct thread_struct {
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/* cached TLS descriptors. */
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struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
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unsigned long esp0;
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unsigned long sysenter_cs;
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unsigned long eip;
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unsigned long esp;
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unsigned long fs;
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unsigned long gs;
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/* Hardware debugging registers */
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unsigned long debugreg[8]; /* %%db0-7 debug registers */
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/* fault info */
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unsigned long cr2, trap_no, error_code;
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/* floating point info */
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union i387_union i387;
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/* virtual 86 mode info */
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struct vm86_struct __user * vm86_info;
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unsigned long screen_bitmap;
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unsigned long v86flags, v86mask, saved_esp0;
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unsigned int saved_fs, saved_gs;
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/* IO permissions */
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unsigned long *io_bitmap_ptr;
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/* max allowed port in the bitmap, in bytes: */
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unsigned long io_bitmap_max;
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};
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#define INIT_THREAD { \
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.vm86_info = NULL, \
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.sysenter_cs = __KERNEL_CS, \
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.io_bitmap_ptr = NULL, \
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}
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/*
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* Note that the .io_bitmap member must be extra-big. This is because
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* the CPU will access an additional byte beyond the end of the IO
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* permission bitmap. The extra byte must be all 1 bits, and must
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* be within the limit.
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*/
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#define INIT_TSS { \
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.esp0 = sizeof(init_stack) + (long)&init_stack, \
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.ss0 = __KERNEL_DS, \
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.ss1 = __KERNEL_CS, \
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.ldt = GDT_ENTRY_LDT, \
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.io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
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.io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
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}
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static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
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{
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tss->esp0 = thread->esp0;
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/* This can only happen when SEP is enabled, no need to test "SEP"arately */
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|
if (unlikely(tss->ss1 != thread->sysenter_cs)) {
|
|
tss->ss1 = thread->sysenter_cs;
|
|
wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
|
|
}
|
|
}
|
|
|
|
#define start_thread(regs, new_eip, new_esp) do { \
|
|
__asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
|
|
set_fs(USER_DS); \
|
|
regs->xds = __USER_DS; \
|
|
regs->xes = __USER_DS; \
|
|
regs->xss = __USER_DS; \
|
|
regs->xcs = __USER_CS; \
|
|
regs->eip = new_eip; \
|
|
regs->esp = new_esp; \
|
|
} while (0)
|
|
|
|
/*
|
|
* This special macro can be used to load a debugging register
|
|
*/
|
|
#define loaddebug(thread,register) \
|
|
__asm__("movl %0,%%db" #register \
|
|
: /* no output */ \
|
|
:"r" ((thread)->debugreg[register]))
|
|
|
|
/* Forward declaration, a strange C thing */
|
|
struct task_struct;
|
|
struct mm_struct;
|
|
|
|
/* Free all resources held by a thread. */
|
|
extern void release_thread(struct task_struct *);
|
|
|
|
/* Prepare to copy thread state - unlazy all lazy status */
|
|
extern void prepare_to_copy(struct task_struct *tsk);
|
|
|
|
/*
|
|
* create a kernel thread without removing it from tasklists
|
|
*/
|
|
extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
|
|
|
|
extern unsigned long thread_saved_pc(struct task_struct *tsk);
|
|
void show_trace(struct task_struct *task, unsigned long *stack);
|
|
|
|
unsigned long get_wchan(struct task_struct *p);
|
|
|
|
#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
|
|
#define KSTK_TOP(info) \
|
|
({ \
|
|
unsigned long *__ptr = (unsigned long *)(info); \
|
|
(unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
|
|
})
|
|
|
|
#define task_pt_regs(task) \
|
|
({ \
|
|
struct pt_regs *__regs__; \
|
|
__regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
|
|
__regs__ - 1; \
|
|
})
|
|
|
|
#define KSTK_EIP(task) (task_pt_regs(task)->eip)
|
|
#define KSTK_ESP(task) (task_pt_regs(task)->esp)
|
|
|
|
|
|
struct microcode_header {
|
|
unsigned int hdrver;
|
|
unsigned int rev;
|
|
unsigned int date;
|
|
unsigned int sig;
|
|
unsigned int cksum;
|
|
unsigned int ldrver;
|
|
unsigned int pf;
|
|
unsigned int datasize;
|
|
unsigned int totalsize;
|
|
unsigned int reserved[3];
|
|
};
|
|
|
|
struct microcode {
|
|
struct microcode_header hdr;
|
|
unsigned int bits[0];
|
|
};
|
|
|
|
typedef struct microcode microcode_t;
|
|
typedef struct microcode_header microcode_header_t;
|
|
|
|
/* microcode format is extended from prescott processors */
|
|
struct extended_signature {
|
|
unsigned int sig;
|
|
unsigned int pf;
|
|
unsigned int cksum;
|
|
};
|
|
|
|
struct extended_sigtable {
|
|
unsigned int count;
|
|
unsigned int cksum;
|
|
unsigned int reserved[3];
|
|
struct extended_signature sigs[0];
|
|
};
|
|
/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
|
|
#define MICROCODE_IOCFREE _IO('6',0)
|
|
|
|
/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
|
|
static inline void rep_nop(void)
|
|
{
|
|
__asm__ __volatile__("rep;nop": : :"memory");
|
|
}
|
|
|
|
#define cpu_relax() rep_nop()
|
|
|
|
/* generic versions from gas */
|
|
#define GENERIC_NOP1 ".byte 0x90\n"
|
|
#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
|
|
#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
|
|
#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
|
|
#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
|
|
#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
|
|
#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
|
|
#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
|
|
|
|
/* Opteron nops */
|
|
#define K8_NOP1 GENERIC_NOP1
|
|
#define K8_NOP2 ".byte 0x66,0x90\n"
|
|
#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
|
|
#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
|
|
#define K8_NOP5 K8_NOP3 K8_NOP2
|
|
#define K8_NOP6 K8_NOP3 K8_NOP3
|
|
#define K8_NOP7 K8_NOP4 K8_NOP3
|
|
#define K8_NOP8 K8_NOP4 K8_NOP4
|
|
|
|
/* K7 nops */
|
|
/* uses eax dependencies (arbitary choice) */
|
|
#define K7_NOP1 GENERIC_NOP1
|
|
#define K7_NOP2 ".byte 0x8b,0xc0\n"
|
|
#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
|
|
#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
|
|
#define K7_NOP5 K7_NOP4 ASM_NOP1
|
|
#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
|
|
#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
|
|
#define K7_NOP8 K7_NOP7 ASM_NOP1
|
|
|
|
#ifdef CONFIG_MK8
|
|
#define ASM_NOP1 K8_NOP1
|
|
#define ASM_NOP2 K8_NOP2
|
|
#define ASM_NOP3 K8_NOP3
|
|
#define ASM_NOP4 K8_NOP4
|
|
#define ASM_NOP5 K8_NOP5
|
|
#define ASM_NOP6 K8_NOP6
|
|
#define ASM_NOP7 K8_NOP7
|
|
#define ASM_NOP8 K8_NOP8
|
|
#elif defined(CONFIG_MK7)
|
|
#define ASM_NOP1 K7_NOP1
|
|
#define ASM_NOP2 K7_NOP2
|
|
#define ASM_NOP3 K7_NOP3
|
|
#define ASM_NOP4 K7_NOP4
|
|
#define ASM_NOP5 K7_NOP5
|
|
#define ASM_NOP6 K7_NOP6
|
|
#define ASM_NOP7 K7_NOP7
|
|
#define ASM_NOP8 K7_NOP8
|
|
#else
|
|
#define ASM_NOP1 GENERIC_NOP1
|
|
#define ASM_NOP2 GENERIC_NOP2
|
|
#define ASM_NOP3 GENERIC_NOP3
|
|
#define ASM_NOP4 GENERIC_NOP4
|
|
#define ASM_NOP5 GENERIC_NOP5
|
|
#define ASM_NOP6 GENERIC_NOP6
|
|
#define ASM_NOP7 GENERIC_NOP7
|
|
#define ASM_NOP8 GENERIC_NOP8
|
|
#endif
|
|
|
|
#define ASM_NOP_MAX 8
|
|
|
|
/* Prefetch instructions for Pentium III and AMD Athlon */
|
|
/* It's not worth to care about 3dnow! prefetches for the K6
|
|
because they are microcoded there and very slow.
|
|
However we don't do prefetches for pre XP Athlons currently
|
|
That should be fixed. */
|
|
#define ARCH_HAS_PREFETCH
|
|
extern inline void prefetch(const void *x)
|
|
{
|
|
alternative_input(ASM_NOP4,
|
|
"prefetchnta (%1)",
|
|
X86_FEATURE_XMM,
|
|
"r" (x));
|
|
}
|
|
|
|
#define ARCH_HAS_PREFETCH
|
|
#define ARCH_HAS_PREFETCHW
|
|
#define ARCH_HAS_SPINLOCK_PREFETCH
|
|
|
|
/* 3dnow! prefetch to get an exclusive cache line. Useful for
|
|
spinlocks to avoid one state transition in the cache coherency protocol. */
|
|
extern inline void prefetchw(const void *x)
|
|
{
|
|
alternative_input(ASM_NOP4,
|
|
"prefetchw (%1)",
|
|
X86_FEATURE_3DNOW,
|
|
"r" (x));
|
|
}
|
|
#define spin_lock_prefetch(x) prefetchw(x)
|
|
|
|
extern void select_idle_routine(const struct cpuinfo_x86 *c);
|
|
|
|
#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
|
|
|
|
extern unsigned long boot_option_idle_override;
|
|
|
|
#endif /* __ASM_I386_PROCESSOR_H */
|