forked from luck/tmp_suning_uos_patched
a98ca73ee3
Once we select SPARSE_IRQ, the interrupt numbers defined in mach/irqs.h will only signify the hardware interrupt offsets, not the interrupt numbers seen by linux. Introduce a wrapper macro that translates the hwirq number to virtual numbers. For now it's just a dummy. Use that macro when specifying the interrupts in resources for platform devices. Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* TI DaVinci Audio definitions
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*/
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#ifndef __ASM_ARCH_DAVINCI_ASP_H
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#define __ASM_ARCH_DAVINCI_ASP_H
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/* Bases of dm644x and dm355 register banks */
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#define DAVINCI_ASP0_BASE 0x01E02000
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#define DAVINCI_ASP1_BASE 0x01E04000
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/* Bases of dm365 register banks */
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#define DAVINCI_DM365_ASP0_BASE 0x01D02000
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/* Bases of dm646x register banks */
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#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000
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#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800
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/* Bases of da850/da830 McASP0 register banks */
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#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000
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/* Bases of da830 McASP1 register banks */
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#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000
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/* Bases of da830 McASP2 register banks */
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#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000
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/* EDMA channels of dm644x and dm355 */
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#define DAVINCI_DMA_ASP0_TX 2
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#define DAVINCI_DMA_ASP0_RX 3
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#define DAVINCI_DMA_ASP1_TX 8
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#define DAVINCI_DMA_ASP1_RX 9
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/* EDMA channels of dm646x */
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#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6
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#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9
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#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12
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/* EDMA channels of da850/da830 McASP0 */
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#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0
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#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1
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/* EDMA channels of da830 McASP1 */
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#define DAVINCI_DA830_DMA_MCASP1_AREVT 2
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#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3
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/* EDMA channels of da830 McASP2 */
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#define DAVINCI_DA830_DMA_MCASP2_AREVT 4
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#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5
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/* Interrupts */
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#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
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#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
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#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT)
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#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT)
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#endif /* __ASM_ARCH_DAVINCI_ASP_H */
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