forked from luck/tmp_suning_uos_patched
1796316a8b
Impact: cleanup, code robustization The __swp_...() macros silently relied upon which bits are used for _PAGE_FILE and _PAGE_PROTNONE. After having changed _PAGE_PROTNONE in our Xen kernel to no longer overlap _PAGE_PAT, live locks and crashes were reported that could have been avoided if these macros properly used the symbolic constants. Since, as pointed out earlier, for Xen Dom0 support mainline likewise will need to eliminate the conflict between _PAGE_PAT and _PAGE_PROTNONE, this patch does all the necessary adjustments, plus it introduces a mechanism to check consistency between MAX_SWAPFILES_SHIFT and the actual encoding macros. This also fixes a latent bug in that x86-64 used a 6-bit mask in __swp_type(), and if MAX_SWAPFILES_SHIFT was increased beyond 5 in (the seemingly unrelated) linux/swap.h, this would have resulted in a collision with _PAGE_FILE. Non-PAE 32-bit code gets similarly adjusted for its pte_to_pgoff() and pgoff_to_pte() calculations. Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
177 lines
4.7 KiB
C
177 lines
4.7 KiB
C
#ifndef _ASM_X86_PGTABLE_3LEVEL_H
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#define _ASM_X86_PGTABLE_3LEVEL_H
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/*
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* Intel Physical Address Extension (PAE) Mode - three-level page
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* tables on PPro+ CPUs.
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*
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* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
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*/
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#define pte_ERROR(e) \
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printk("%s:%d: bad pte %p(%08lx%08lx).\n", \
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__FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
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#define pmd_ERROR(e) \
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printk("%s:%d: bad pmd %p(%016Lx).\n", \
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__FILE__, __LINE__, &(e), pmd_val(e))
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#define pgd_ERROR(e) \
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printk("%s:%d: bad pgd %p(%016Lx).\n", \
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__FILE__, __LINE__, &(e), pgd_val(e))
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static inline int pud_none(pud_t pud)
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{
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return pud_val(pud) == 0;
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}
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static inline int pud_bad(pud_t pud)
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{
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return (pud_val(pud) & ~(PTE_PFN_MASK | _KERNPG_TABLE | _PAGE_USER)) != 0;
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}
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static inline int pud_present(pud_t pud)
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{
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return pud_val(pud) & _PAGE_PRESENT;
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}
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/* Rules for using set_pte: the pte being assigned *must* be
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* either not present or in a state where the hardware will
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* not attempt to update the pte. In places where this is
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* not possible, use pte_get_and_clear to obtain the old pte
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* value and then use set_pte to update it. -ben
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*/
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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{
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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/*
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* Since this is only called on user PTEs, and the page fault handler
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* must handle the already racy situation of simultaneous page faults,
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* we are justified in merely clearing the PTE present bit, followed
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* by a set. The ordering here is important.
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*/
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static inline void native_set_pte_present(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, pte_t pte)
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{
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ptep->pte_low = 0;
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smp_wmb();
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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set_64bit((unsigned long long *)(ptep), native_pte_val(pte));
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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set_64bit((unsigned long long *)(pmdp), native_pmd_val(pmd));
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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set_64bit((unsigned long long *)(pudp), native_pud_val(pud));
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}
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/*
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* For PTEs and PDEs, we must clear the P-bit first when clearing a page table
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* entry, so clear the bottom half first and enforce ordering with a compiler
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* barrier.
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*/
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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ptep->pte_low = 0;
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smp_wmb();
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ptep->pte_high = 0;
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}
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static inline void native_pmd_clear(pmd_t *pmd)
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{
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u32 *tmp = (u32 *)pmd;
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*tmp = 0;
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smp_wmb();
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*(tmp + 1) = 0;
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}
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static inline void pud_clear(pud_t *pudp)
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{
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unsigned long pgd;
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set_pud(pudp, __pud(0));
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/*
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* According to Intel App note "TLBs, Paging-Structure Caches,
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* and Their Invalidation", April 2007, document 317080-001,
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* section 8.1: in PAE mode we explicitly have to flush the
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* TLB via cr3 if the top-level pgd is changed...
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*
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* Make sure the pud entry we're updating is within the
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* current pgd to avoid unnecessary TLB flushes.
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*/
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pgd = read_cr3();
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if (__pa(pudp) >= pgd && __pa(pudp) <
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(pgd + sizeof(pgd_t)*PTRS_PER_PGD))
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write_cr3(pgd);
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}
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#define pud_page(pud) pfn_to_page(pud_val(pud) >> PAGE_SHIFT)
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#define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & PTE_PFN_MASK))
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/* Find an entry in the second-level page table.. */
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#define pmd_offset(pud, address) ((pmd_t *)pud_page_vaddr(*(pud)) + \
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pmd_index(address))
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#ifdef CONFIG_SMP
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static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
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{
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pte_t res;
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/* xchg acts as a barrier before the setting of the high bits */
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res.pte_low = xchg(&ptep->pte_low, 0);
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res.pte_high = ptep->pte_high;
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ptep->pte_high = 0;
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return res;
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}
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#else
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#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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#endif
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#define __HAVE_ARCH_PTE_SAME
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static inline int pte_same(pte_t a, pte_t b)
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{
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return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
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}
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static inline int pte_none(pte_t pte)
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{
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return !pte.pte_low && !pte.pte_high;
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}
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/*
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* Bits 0, 6 and 7 are taken in the low part of the pte,
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* put the 32 bits of offset into the high part.
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*/
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#define pte_to_pgoff(pte) ((pte).pte_high)
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#define pgoff_to_pte(off) \
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((pte_t) { { .pte_low = _PAGE_FILE, .pte_high = (off) } })
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#define PTE_FILE_MAX_BITS 32
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/* Encode and de-code a swap entry */
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
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#define __swp_type(x) (((x).val) & 0x1f)
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#define __swp_offset(x) ((x).val >> 5)
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#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) << 5})
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#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
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#define __swp_entry_to_pte(x) ((pte_t){ { .pte_high = (x).val } })
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#endif /* _ASM_X86_PGTABLE_3LEVEL_H */
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