forked from luck/tmp_suning_uos_patched
2c799cef4d
This is needed to minimize io.h so the SoC specific io.h for ARMs can removed. Note that minimal driver changes for DSS and RNG are needed to include cpu.h for SoC detection macros. Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Matt Mackall <mpm@selenic.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Tony Lindgren <tony@atomide.com>
131 lines
4.9 KiB
C
131 lines
4.9 KiB
C
/*
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* opp2420_data.c - old-style "OPP" table for OMAP2420
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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* Copyright (C) 2004-2009 Nokia Corporation
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*
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
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* These configurations are characterized by voltage and speed for clocks.
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* The device is only validated for certain combinations. One way to express
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* these combinations is via the 'ratios' which the clocks operate with
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* respect to each other. These ratio sets are for a given voltage/DPLL
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* setting. All configurations can be described by a DPLL setting and a ratio.
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*
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* XXX Missing voltage data.
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* XXX Missing 19.2MHz sys_clk rate sets (needed for N800/N810)
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*
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* THe format described in this file is deprecated. Once a reasonable
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* OPP API exists, the data in this file should be converted to use it.
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*
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* This is technically part of the OMAP2xxx clock code.
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*
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* Considerable work is still needed to fully support dynamic frequency
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* changes on OMAP2xxx-series chips. Readers interested in such a
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* project are encouraged to review the Maemo Diablo RX-34 and RX-44
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* kernel source at:
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* http://repository.maemo.org/pool/diablo/free/k/kernel-source-diablo/
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*/
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#include <plat/hardware.h>
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#include "opp2xxx.h"
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#include "sdrc.h"
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#include "clock.h"
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/*
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* Key dividers which make up a PRCM set. Ratios for a PRCM are mandated.
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* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
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* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
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* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
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*
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* Filling in table based on H4 boards available. There are quite a
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* few more rate combinations which could be defined.
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*
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* When multiple values are defined the start up will try and choose
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* the fastest one. If a 'fast' value is defined, then automatically,
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* the /2 one should be included as it can be used. Generally having
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* more than one fast set does not make sense, as static timings need
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* to be changed to change the set. The exception is the bypass
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* setting which is available for low power bypass.
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*
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* Note: This table needs to be sorted, fastest to slowest.
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**/
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const struct prcm_config omap2420_rate_table[] = {
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/* PRCM I - FAST */
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{S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
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RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
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RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
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RATE_IN_242X},
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/* PRCM II - FAST */
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{S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
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RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
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RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
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RATE_IN_242X},
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{S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
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RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
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RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
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RATE_IN_242X},
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/* PRCM III - FAST */
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{S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
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RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
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RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
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RATE_IN_242X},
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{S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
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RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
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RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
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RATE_IN_242X},
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/* PRCM II - SLOW */
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{S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
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RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
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RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
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RATE_IN_242X},
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{S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
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RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
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RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
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RATE_IN_242X},
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/* PRCM III - SLOW */
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{S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
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RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
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RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
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RATE_IN_242X},
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{S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
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RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
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RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
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RATE_IN_242X},
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/* PRCM-VII (boot-bypass) */
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{S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
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RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
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RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
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RATE_IN_242X},
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/* PRCM-VII (boot-bypass) */
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{S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
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RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
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RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
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MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
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RATE_IN_242X},
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
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};
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