David S. Miller 4ba991d3eb sparc: Detect and handle UltraSPARC-T3 cpu types. ... The cpu compatible string we look for is "SPARC-T3". As far as memset/memcpy optimizations go, we treat this chip the same as Niagara-T2/T2+. Use cache initializing stores for memset, and use perfetch, FPU block loads, cache initializing stores, and block stores for copies. We use the Niagara-T2 perf support, since T3 is a close relative in this regard. Later we'll add support for the new events T3 can report, plus enable T3's new "sample" mode. For now I haven't added any new ELF hwcap flags. We probably need to add a couple, for example: T2 and T3 both support the population count instruction in hardware. T3 supports VIS3 instructions, including support (finally) for partitioned shift. One can also now move directly between float and integer registers. T3 supports instructions meant to help with Galois Field and other HPC calculations, such as XOR multiply. Also there are "OP and negate" instructions, for example "fnmul" which is multiply-and-negate. T3 recognizes the transactional memory opcodes, however since transactional memory isn't supported: 1) 'commit' behaves as a NOP and 2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps' behaves as a NOP. So we'll need about 3 new elf capability flags in the end to represent all of these things. Signed-off-by: David S. Miller <davem@davemloft.net>		2011-07-27 22:10:10 -07:00
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boot
configs
include/asm	sparc: Detect and handle UltraSPARC-T3 cpu types.	2011-07-27 22:10:10 -07:00
kernel	sparc: Detect and handle UltraSPARC-T3 cpu types.	2011-07-27 22:10:10 -07:00
lib	sparc: rename atomic_add_unless	2011-07-27 12:53:36 -07:00
math-emu	perf: Remove the nmi parameter from the swevent and overflow interface	2011-07-01 11:06:35 +02:00
mm	sparc64: implement get_user_pages_fast()	2011-07-25 20:57:10 -07:00
oprofile
prom	sparc: Remove unnecessary semicolons	2011-06-07 16:06:34 -07:00
Kconfig	sparc64: use RCU page table freeing	2011-07-25 20:57:10 -07:00
Kconfig.debug
Makefile