forked from luck/tmp_suning_uos_patched
6b32fafee2
Also add a few definitions that were missing. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
116 lines
3.6 KiB
C
116 lines
3.6 KiB
C
/*
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* Header for the new SH dmaengine driver
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef SH_DMA_H
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#define SH_DMA_H
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#include <linux/dmaengine.h>
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#include <linux/list.h>
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#include <linux/shdma-base.h>
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#include <linux/types.h>
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struct device;
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/* Used by slave DMA clients to request DMA to/from a specific peripheral */
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struct sh_dmae_slave {
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struct shdma_slave shdma_slave; /* Set by the platform */
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};
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/*
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* Supplied by platforms to specify, how a DMA channel has to be configured for
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* a certain peripheral
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*/
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struct sh_dmae_slave_config {
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int slave_id;
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dma_addr_t addr;
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u32 chcr;
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char mid_rid;
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};
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/**
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* struct sh_dmae_channel - DMAC channel platform data
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* @offset: register offset within the main IOMEM resource
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* @dmars: channel DMARS register offset
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* @chclr_offset: channel CHCLR register offset
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* @dmars_bit: channel DMARS field offset within the register
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* @chclr_bit: bit position, to be set to reset the channel
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*/
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struct sh_dmae_channel {
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unsigned int offset;
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unsigned int dmars;
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unsigned int chclr_offset;
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unsigned char dmars_bit;
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unsigned char chclr_bit;
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};
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/**
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* struct sh_dmae_pdata - DMAC platform data
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* @slave: array of slaves
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* @slave_num: number of slaves in the above array
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* @channel: array of DMA channels
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* @channel_num: number of channels in the above array
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* @ts_low_shift: shift of the low part of the TS field
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* @ts_low_mask: low TS field mask
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* @ts_high_shift: additional shift of the high part of the TS field
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* @ts_high_mask: high TS field mask
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* @ts_shift: array of Transfer Size shifts, indexed by TS value
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* @ts_shift_num: number of shifts in the above array
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* @dmaor_init: DMAOR initialisation value
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* @chcr_offset: CHCR address offset
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* @chcr_ie_bit: CHCR Interrupt Enable bit
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* @dmaor_is_32bit: DMAOR is a 32-bit register
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* @needs_tend_set: the TEND register has to be set
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* @no_dmars: DMAC has no DMARS registers
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* @chclr_present: DMAC has one or several CHCLR registers
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* @chclr_bitwise: channel CHCLR registers are bitwise
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* @slave_only: DMAC cannot be used for MEMCPY
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*/
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struct sh_dmae_pdata {
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const struct sh_dmae_slave_config *slave;
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int slave_num;
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const struct sh_dmae_channel *channel;
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int channel_num;
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unsigned int ts_low_shift;
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unsigned int ts_low_mask;
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unsigned int ts_high_shift;
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unsigned int ts_high_mask;
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const unsigned int *ts_shift;
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int ts_shift_num;
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u16 dmaor_init;
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unsigned int chcr_offset;
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u32 chcr_ie_bit;
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unsigned int dmaor_is_32bit:1;
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unsigned int needs_tend_set:1;
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unsigned int no_dmars:1;
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unsigned int chclr_present:1;
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unsigned int chclr_bitwise:1;
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unsigned int slave_only:1;
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};
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004 /* Address Error Flag */
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001 /* DMA Master Enable */
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/* Definitions for the SuperH DMAC */
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#define DM_INC 0x00004000 /* Destination addresses are incremented */
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#define DM_DEC 0x00008000 /* Destination addresses are decremented */
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#define DM_FIX 0x0000c000 /* Destination address is fixed */
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#define SM_INC 0x00001000 /* Source addresses are incremented */
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#define SM_DEC 0x00002000 /* Source addresses are decremented */
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#define SM_FIX 0x00003000 /* Source address is fixed */
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#define RS_AUTO 0x00000400 /* Auto Request */
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#define RS_ERS 0x00000800 /* DMA extended resource selector */
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#define CHCR_DE 0x00000001 /* DMA Enable */
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#define CHCR_TE 0x00000002 /* Transfer End Flag */
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#define CHCR_IE 0x00000004 /* Interrupt Enable */
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#endif
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