forked from luck/tmp_suning_uos_patched
550 lines
13 KiB
C
550 lines
13 KiB
C
/*
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* OMAP2 Power Management Routines
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*
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Copyright (C) 2006-2008 Nokia Corporation
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*
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* Written by:
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* Richard Woodruff <r-woodruff2@ti.com>
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* Tony Lindgren
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* Juha Yrjola
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* Amit Kucheria <amit.kucheria@nokia.com>
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* Igor Stoppa <igor.stoppa@nokia.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/suspend.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/interrupt.h>
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#include <linux/sysfs.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/time.h>
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#include <linux/gpio.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/mach-types.h>
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#include <mach/irqs.h>
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#include <mach/clock.h>
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#include <mach/sram.h>
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#include <mach/control.h>
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#include <mach/mux.h>
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#include <mach/dma.h>
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#include <mach/board.h>
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "cm.h"
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#include "cm-regbits-24xx.h"
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#include "sdrc.h"
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#include "pm.h"
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#include <mach/powerdomain.h>
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#include <mach/clockdomain.h>
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static void (*omap2_sram_idle)(void);
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static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
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void __iomem *sdrc_power);
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static struct powerdomain *mpu_pwrdm;
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static struct powerdomain *core_pwrdm;
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static struct clockdomain *dsp_clkdm;
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static struct clockdomain *gfx_clkdm;
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static struct clk *osc_ck, *emul_ck;
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static int omap2_fclks_active(void)
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{
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u32 f1, f2;
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f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
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/* Ignore UART clocks. These are handled by UART core (serial.c) */
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f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
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f2 &= ~OMAP24XX_EN_UART3;
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if (f1 | f2)
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return 1;
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return 0;
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}
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static void omap2_enter_full_retention(void)
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{
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u32 l;
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struct timespec ts_preidle, ts_postidle, ts_idle;
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/* There is 1 reference hold for all children of the oscillator
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* clock, the following will remove it. If no one else uses the
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* oscillator itself it will be disabled if/when we enter retention
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* mode.
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*/
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clk_disable(osc_ck);
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/* Clear old wake-up events */
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/* REVISIT: These write to reserved bits? */
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prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
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prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
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prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
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/*
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* Set MPU powerdomain's next power state to RETENTION;
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* preserve logic state during retention
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*/
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pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
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/* Workaround to kill USB */
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l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
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omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
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omap2_gpio_prepare_for_retention();
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if (omap2_pm_debug) {
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omap2_pm_dump(0, 0, 0);
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getnstimeofday(&ts_preidle);
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}
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/* One last check for pending IRQs to avoid extra latency due
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* to sleeping unnecessarily. */
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if (omap_irq_pending())
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goto no_sleep;
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omap_uart_prepare_idle(0);
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omap_uart_prepare_idle(1);
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omap_uart_prepare_idle(2);
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/* Jump to SRAM suspend code */
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omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
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OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
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OMAP_SDRC_REGADDR(SDRC_POWER));
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omap_uart_resume_idle(2);
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omap_uart_resume_idle(1);
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omap_uart_resume_idle(0);
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no_sleep:
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if (omap2_pm_debug) {
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unsigned long long tmp;
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getnstimeofday(&ts_postidle);
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ts_idle = timespec_sub(ts_postidle, ts_preidle);
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tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
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omap2_pm_dump(0, 1, tmp);
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}
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omap2_gpio_resume_after_retention();
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clk_enable(osc_ck);
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/* clear CORE wake-up events */
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prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
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prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
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/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
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prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
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/* MPU domain wake events */
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l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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if (l & 0x01)
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prm_write_mod_reg(0x01, OCP_MOD,
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OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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if (l & 0x20)
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prm_write_mod_reg(0x20, OCP_MOD,
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OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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/* Mask future PRCM-to-MPU interrupts */
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prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
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}
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static int omap2_i2c_active(void)
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{
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u32 l;
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l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
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}
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static int sti_console_enabled;
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static int omap2_allow_mpu_retention(void)
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{
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u32 l;
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/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
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l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
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OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
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OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
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return 0;
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/* Check for UART3. */
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l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
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if (l & OMAP24XX_EN_UART3)
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return 0;
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if (sti_console_enabled)
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return 0;
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return 1;
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}
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static void omap2_enter_mpu_retention(void)
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{
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int only_idle = 0;
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struct timespec ts_preidle, ts_postidle, ts_idle;
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/* Putting MPU into the WFI state while a transfer is active
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* seems to cause the I2C block to timeout. Why? Good question. */
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if (omap2_i2c_active())
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return;
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/* The peripherals seem not to be able to wake up the MPU when
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* it is in retention mode. */
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if (omap2_allow_mpu_retention()) {
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/* REVISIT: These write to reserved bits? */
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prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
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prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
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prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
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/* Try to enter MPU retention */
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prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
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OMAP_LOGICRETSTATE,
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MPU_MOD, PM_PWSTCTRL);
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} else {
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/* Block MPU retention */
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prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD, PM_PWSTCTRL);
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only_idle = 1;
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}
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if (omap2_pm_debug) {
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omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
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getnstimeofday(&ts_preidle);
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}
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omap2_sram_idle();
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if (omap2_pm_debug) {
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unsigned long long tmp;
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getnstimeofday(&ts_postidle);
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ts_idle = timespec_sub(ts_postidle, ts_preidle);
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tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
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omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
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}
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}
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static int omap2_can_sleep(void)
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{
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if (omap2_fclks_active())
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return 0;
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if (osc_ck->usecount > 1)
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return 0;
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if (omap_dma_running())
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return 0;
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return 1;
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}
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static void omap2_pm_idle(void)
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{
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local_irq_disable();
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local_fiq_disable();
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if (!omap2_can_sleep()) {
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if (omap_irq_pending())
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goto out;
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omap2_enter_mpu_retention();
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goto out;
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}
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if (omap_irq_pending())
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goto out;
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omap2_enter_full_retention();
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out:
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local_fiq_enable();
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local_irq_enable();
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}
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static int omap2_pm_prepare(void)
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{
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/* We cannot sleep in idle until we have resumed */
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disable_hlt();
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return 0;
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}
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static int omap2_pm_suspend(void)
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{
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u32 wken_wkup, mir1;
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wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
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prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
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/* Mask GPT1 */
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mir1 = omap_readl(0x480fe0a4);
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omap_writel(1 << 5, 0x480fe0ac);
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omap_uart_prepare_suspend();
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omap2_enter_full_retention();
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omap_writel(mir1, 0x480fe0a4);
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prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
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return 0;
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}
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static int omap2_pm_enter(suspend_state_t state)
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{
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int ret = 0;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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ret = omap2_pm_suspend();
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static void omap2_pm_finish(void)
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{
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enable_hlt();
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}
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static struct platform_suspend_ops omap_pm_ops = {
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.prepare = omap2_pm_prepare,
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.enter = omap2_pm_enter,
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.finish = omap2_pm_finish,
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.valid = suspend_valid_only_mem,
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};
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static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm)
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{
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omap2_clkdm_allow_idle(clkdm);
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return 0;
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}
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static void __init prcm_setup_regs(void)
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{
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int i, num_mem_banks;
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struct powerdomain *pwrdm;
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/* Enable autoidle */
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prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
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OMAP2_PRCM_SYSCONFIG_OFFSET);
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/* Set all domain wakeup dependencies */
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prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
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prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
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prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
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prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
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if (cpu_is_omap2430())
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prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
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/*
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* Set CORE powerdomain memory banks to retain their contents
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* during RETENTION
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*/
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num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
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for (i = 0; i < num_mem_banks; i++)
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pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
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/* Set CORE powerdomain's next power state to RETENTION */
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pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
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/*
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* Set MPU powerdomain's next power state to RETENTION;
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* preserve logic state during retention
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*/
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pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
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/* Force-power down DSP, GFX powerdomains */
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pwrdm = clkdm_get_pwrdm(dsp_clkdm);
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pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
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omap2_clkdm_sleep(dsp_clkdm);
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pwrdm = clkdm_get_pwrdm(gfx_clkdm);
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pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
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omap2_clkdm_sleep(gfx_clkdm);
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/* Enable clockdomain hardware-supervised control for all clkdms */
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clkdm_for_each(_pm_clkdm_enable_hwsup);
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/* Enable clock autoidle for all domains */
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cm_write_mod_reg(OMAP24XX_AUTO_CAM |
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OMAP24XX_AUTO_MAILBOXES |
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OMAP24XX_AUTO_WDT4 |
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OMAP2420_AUTO_WDT3 |
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OMAP24XX_AUTO_MSPRO |
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OMAP2420_AUTO_MMC |
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OMAP24XX_AUTO_FAC |
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OMAP2420_AUTO_EAC |
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OMAP24XX_AUTO_HDQ |
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OMAP24XX_AUTO_UART2 |
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OMAP24XX_AUTO_UART1 |
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OMAP24XX_AUTO_I2C2 |
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OMAP24XX_AUTO_I2C1 |
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OMAP24XX_AUTO_MCSPI2 |
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OMAP24XX_AUTO_MCSPI1 |
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OMAP24XX_AUTO_MCBSP2 |
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OMAP24XX_AUTO_MCBSP1 |
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OMAP24XX_AUTO_GPT12 |
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OMAP24XX_AUTO_GPT11 |
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OMAP24XX_AUTO_GPT10 |
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OMAP24XX_AUTO_GPT9 |
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OMAP24XX_AUTO_GPT8 |
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OMAP24XX_AUTO_GPT7 |
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OMAP24XX_AUTO_GPT6 |
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OMAP24XX_AUTO_GPT5 |
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OMAP24XX_AUTO_GPT4 |
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OMAP24XX_AUTO_GPT3 |
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OMAP24XX_AUTO_GPT2 |
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OMAP2420_AUTO_VLYNQ |
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OMAP24XX_AUTO_DSS,
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CORE_MOD, CM_AUTOIDLE1);
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cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
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OMAP24XX_AUTO_SSI |
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OMAP24XX_AUTO_USB,
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CORE_MOD, CM_AUTOIDLE2);
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cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
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OMAP24XX_AUTO_GPMC |
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OMAP24XX_AUTO_SDMA,
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CORE_MOD, CM_AUTOIDLE3);
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cm_write_mod_reg(OMAP24XX_AUTO_PKA |
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OMAP24XX_AUTO_AES |
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OMAP24XX_AUTO_RNG |
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OMAP24XX_AUTO_SHA |
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OMAP24XX_AUTO_DES,
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CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
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cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
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/* Put DPLL and both APLLs into autoidle mode */
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cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
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(0x03 << OMAP24XX_AUTO_96M_SHIFT) |
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(0x03 << OMAP24XX_AUTO_54M_SHIFT),
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PLL_MOD, CM_AUTOIDLE);
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cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
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OMAP24XX_AUTO_WDT1 |
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OMAP24XX_AUTO_MPU_WDT |
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OMAP24XX_AUTO_GPIOS |
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OMAP24XX_AUTO_32KSYNC |
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OMAP24XX_AUTO_GPT1,
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WKUP_MOD, CM_AUTOIDLE);
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/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
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* stabilisation */
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prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
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OMAP2_PRCM_CLKSSETUP_OFFSET);
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/* Configure automatic voltage transition */
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prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
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OMAP2_PRCM_VOLTSETUP_OFFSET);
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prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
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(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
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OMAP24XX_MEMRETCTRL |
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(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
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(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
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OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
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/* Enable wake-up events */
|
|
prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
|
|
WKUP_MOD, PM_WKEN);
|
|
}
|
|
|
|
static int __init omap2_pm_init(void)
|
|
{
|
|
u32 l;
|
|
|
|
if (!cpu_is_omap24xx())
|
|
return -ENODEV;
|
|
|
|
printk(KERN_INFO "Power Management for OMAP2 initializing\n");
|
|
l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
|
|
printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
|
|
|
|
/* Look up important powerdomains, clockdomains */
|
|
|
|
mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
|
|
if (!mpu_pwrdm)
|
|
pr_err("PM: mpu_pwrdm not found\n");
|
|
|
|
core_pwrdm = pwrdm_lookup("core_pwrdm");
|
|
if (!core_pwrdm)
|
|
pr_err("PM: core_pwrdm not found\n");
|
|
|
|
dsp_clkdm = clkdm_lookup("dsp_clkdm");
|
|
if (!dsp_clkdm)
|
|
pr_err("PM: mpu_clkdm not found\n");
|
|
|
|
gfx_clkdm = clkdm_lookup("gfx_clkdm");
|
|
if (!gfx_clkdm)
|
|
pr_err("PM: gfx_clkdm not found\n");
|
|
|
|
|
|
osc_ck = clk_get(NULL, "osc_ck");
|
|
if (IS_ERR(osc_ck)) {
|
|
printk(KERN_ERR "could not get osc_ck\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (cpu_is_omap242x()) {
|
|
emul_ck = clk_get(NULL, "emul_ck");
|
|
if (IS_ERR(emul_ck)) {
|
|
printk(KERN_ERR "could not get emul_ck\n");
|
|
clk_put(osc_ck);
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
prcm_setup_regs();
|
|
|
|
/* Hack to prevent MPU retention when STI console is enabled. */
|
|
{
|
|
const struct omap_sti_console_config *sti;
|
|
|
|
sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
|
|
struct omap_sti_console_config);
|
|
if (sti != NULL && sti->enable)
|
|
sti_console_enabled = 1;
|
|
}
|
|
|
|
/*
|
|
* We copy the assembler sleep/wakeup routines to SRAM.
|
|
* These routines need to be in SRAM as that's the only
|
|
* memory the MPU can see when it wakes up.
|
|
*/
|
|
if (cpu_is_omap24xx()) {
|
|
omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
|
|
omap24xx_idle_loop_suspend_sz);
|
|
|
|
omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
|
|
omap24xx_cpu_suspend_sz);
|
|
}
|
|
|
|
suspend_set_ops(&omap_pm_ops);
|
|
pm_idle = omap2_pm_idle;
|
|
|
|
return 0;
|
|
}
|
|
|
|
late_initcall(omap2_pm_init);
|