Vincent Chen d18ebc274c riscv: support trap-based WARN() ... The WARN() related function will trigger a debug exception. This can help developers to analyze the cause of WARN() because if the debugger is connected, the control flow will be transferred to debugging environment. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-05-16 20:42:12 -07:00
..
boot	RISC-V: Build flat and compressed kernel images	2018-11-20 05:19:09 -08:00
configs	RISC-V: Add separate defconfig for 32bit systems	2019-04-09 09:42:49 -07:00
include	riscv: support trap-based WARN()	2019-05-16 20:42:12 -07:00
kernel	riscv: move flush_icache_{all,mm} to cacheflush.c	2019-05-16 20:42:12 -07:00
lib	RISC-V: lib: minor asm cleanup	2018-12-21 08:17:02 -08:00
mm	riscv: move switch_mm to its own file	2019-05-16 20:42:12 -07:00
net	bpf, riscv: add BPF JIT for RV64G	2019-02-05 16:56:10 +01:00
Kconfig	riscv: remove CONFIG_RISCV_ISA_A	2019-04-25 14:51:10 -07:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Makefile	riscv: remove CONFIG_RISCV_ISA_A	2019-04-25 14:51:10 -07:00