Vineet Gupta d1f317d825 ARCv2: MMUv4: cache programming model changes ... Caveats about cache flush on ARCv2 based cores - dcache is PIPT so paddr is sufficient for cache maintenance ops (no need to setup PTAG reg - icache is still VIPT but only aliasing configs need PTAG setup So basically this is departure from MMU-v3 which always need vaddr in line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG, IC_PTAG respectively. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-06-22 14:06:55 +05:30
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cache.c	ARCv2: MMUv4: cache programming model changes	2015-06-22 14:06:55 +05:30
dma.c	ARC: remove the unused platform helpers from dma mapping API	2015-06-19 18:09:23 +05:30
extable.c	ARC: Fix coding style issues	2013-04-09 12:21:14 +05:30
fault.c	ARC: perf: Enable generic software events	2015-02-27 10:15:01 +05:30
init.c	ARC: mem init spring cleaning - No functional changes	2015-04-13 15:16:29 +05:30
ioremap.c	ARC: Use <linux/*> headers instead of <asm/*>	2013-04-09 12:21:14 +05:30
Makefile	ARC: mm/cache_arc700.c -> mm/cache.c	2015-06-19 18:09:32 +05:30
mmap.c	ARC: [mm] Aliasing VIPT dcache support 4/4	2013-05-09 22:00:57 +05:30
tlb.c	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30
tlbex.S	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30