forked from luck/tmp_suning_uos_patched
bcb05504ed
On Tue, 2005-11-15 at 18:52 +0000, David Woodhouse wrote: > This cleanup patch speeds up the null syscall path on ppc64 by about 3%, > and brings the ppc32 and ppc64 code slightly closer together. Needs this unless your binutils, like mine, are clever enough to notice my stupidity and fix it up automatically... Spotted by Paul. Signed-off-by: David Woodhouse <dwmw2@infradead.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
859 lines
19 KiB
ArmAsm
859 lines
19 KiB
ArmAsm
/*
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* arch/ppc64/kernel/entry.S
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*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Adapted for Power Macintosh by Paul Mackerras.
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains the system call entry code, context switch
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* code, and exception/interrupt return code for PowerPC.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/errno.h>
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#include <asm/unistd.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#ifdef CONFIG_PPC_ISERIES
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#define DO_SOFT_DISABLE
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#endif
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/*
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* System calls.
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*/
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.section ".toc","aw"
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.SYS_CALL_TABLE:
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.tc .sys_call_table[TC],.sys_call_table
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/* This value is used to mark exception frames on the stack. */
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exception_marker:
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.tc ID_72656773_68657265[TC],0x7265677368657265
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.section ".text"
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.align 7
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#undef SHOW_SYSCALLS
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.globl system_call_common
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system_call_common:
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andi. r10,r12,MSR_PR
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mr r10,r1
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addi r1,r1,-INT_FRAME_SIZE
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beq- 1f
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ld r1,PACAKSAVE(r13)
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1: std r10,0(r1)
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std r11,_NIP(r1)
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std r12,_MSR(r1)
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std r0,GPR0(r1)
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std r10,GPR1(r1)
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std r2,GPR2(r1)
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std r3,GPR3(r1)
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std r4,GPR4(r1)
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std r5,GPR5(r1)
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std r6,GPR6(r1)
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std r7,GPR7(r1)
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std r8,GPR8(r1)
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li r11,0
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std r11,GPR9(r1)
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std r11,GPR10(r1)
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std r11,GPR11(r1)
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std r11,GPR12(r1)
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std r9,GPR13(r1)
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crclr so
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mfcr r9
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mflr r10
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li r11,0xc01
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std r9,_CCR(r1)
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std r10,_LINK(r1)
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std r11,_TRAP(r1)
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mfxer r9
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mfctr r10
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std r9,_XER(r1)
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std r10,_CTR(r1)
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std r3,ORIG_GPR3(r1)
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ld r2,PACATOC(r13)
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addi r9,r1,STACK_FRAME_OVERHEAD
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ld r11,exception_marker@toc(r2)
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std r11,-16(r9) /* "regshere" marker */
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#ifdef CONFIG_PPC_ISERIES
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/* Hack for handling interrupts when soft-enabling on iSeries */
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cmpdi cr1,r0,0x5555 /* syscall 0x5555 */
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andi. r10,r12,MSR_PR /* from kernel */
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crand 4*cr0+eq,4*cr1+eq,4*cr0+eq
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beq hardware_interrupt_entry
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lbz r10,PACAPROCENABLED(r13)
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std r10,SOFTE(r1)
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#endif
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mfmsr r11
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ori r11,r11,MSR_EE
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mtmsrd r11,1
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#ifdef SHOW_SYSCALLS
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bl .do_show_syscall
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REST_GPR(0,r1)
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REST_4GPRS(3,r1)
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REST_2GPRS(7,r1)
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addi r9,r1,STACK_FRAME_OVERHEAD
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#endif
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clrrdi r11,r1,THREAD_SHIFT
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ld r10,TI_FLAGS(r11)
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andi. r11,r10,_TIF_SYSCALL_T_OR_A
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bne- syscall_dotrace
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syscall_dotrace_cont:
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cmpldi 0,r0,NR_syscalls
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bge- syscall_enosys
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system_call: /* label this so stack traces look sane */
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/*
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* Need to vector to 32 Bit or default sys_call_table here,
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* based on caller's run-mode / personality.
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*/
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ld r11,.SYS_CALL_TABLE@toc(2)
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andi. r10,r10,_TIF_32BIT
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beq 15f
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addi r11,r11,8 /* use 32-bit syscall entries */
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clrldi r3,r3,32
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clrldi r4,r4,32
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clrldi r5,r5,32
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clrldi r6,r6,32
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clrldi r7,r7,32
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clrldi r8,r8,32
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15:
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slwi r0,r0,4
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ldx r10,r11,r0 /* Fetch system call handler [ptr] */
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mtctr r10
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bctrl /* Call handler */
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syscall_exit:
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std r3,RESULT(r1)
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#ifdef SHOW_SYSCALLS
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bl .do_show_syscall_exit
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ld r3,RESULT(r1)
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#endif
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clrrdi r12,r1,THREAD_SHIFT
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/* disable interrupts so current_thread_info()->flags can't change,
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and so that we don't get interrupted after loading SRR0/1. */
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ld r8,_MSR(r1)
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andi. r10,r8,MSR_RI
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beq- unrecov_restore
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mfmsr r10
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rldicl r10,r10,48,1
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rotldi r10,r10,16
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mtmsrd r10,1
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ld r9,TI_FLAGS(r12)
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li r11,-_LAST_ERRNO
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andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_RESTOREALL|_TIF_SAVE_NVGPRS|_TIF_NOERROR)
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bne- syscall_exit_work
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cmpld r3,r11
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ld r5,_CCR(r1)
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bge- syscall_error
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syscall_error_cont:
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ld r7,_NIP(r1)
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stdcx. r0,0,r1 /* to clear the reservation */
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andi. r6,r8,MSR_PR
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ld r4,_LINK(r1)
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beq- 1f /* only restore r13 if */
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ld r13,GPR13(r1) /* returning to usermode */
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1: ld r2,GPR2(r1)
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li r12,MSR_RI
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andc r11,r10,r12
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mtmsrd r11,1 /* clear MSR.RI */
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ld r1,GPR1(r1)
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mtlr r4
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mtcr r5
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mtspr SPRN_SRR0,r7
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mtspr SPRN_SRR1,r8
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rfid
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b . /* prevent speculative execution */
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syscall_error:
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oris r5,r5,0x1000 /* Set SO bit in CR */
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neg r3,r3
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std r5,_CCR(r1)
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b syscall_error_cont
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/* Traced system call support */
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syscall_dotrace:
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bl .save_nvgprs
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .do_syscall_trace_enter
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ld r0,GPR0(r1) /* Restore original registers */
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ld r3,GPR3(r1)
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ld r4,GPR4(r1)
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ld r5,GPR5(r1)
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ld r6,GPR6(r1)
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ld r7,GPR7(r1)
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ld r8,GPR8(r1)
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addi r9,r1,STACK_FRAME_OVERHEAD
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clrrdi r10,r1,THREAD_SHIFT
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ld r10,TI_FLAGS(r10)
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b syscall_dotrace_cont
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syscall_enosys:
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li r3,-ENOSYS
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b syscall_exit
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syscall_exit_work:
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/* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
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If TIF_NOERROR is set, just save r3 as it is. */
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andi. r0,r9,_TIF_RESTOREALL
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bne- 2f
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cmpld r3,r11 /* r10 is -LAST_ERRNO */
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blt+ 1f
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andi. r0,r9,_TIF_NOERROR
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bne- 1f
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ld r5,_CCR(r1)
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neg r3,r3
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oris r5,r5,0x1000 /* Set SO bit in CR */
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std r5,_CCR(r1)
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1: std r3,GPR3(r1)
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2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
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beq 4f
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/* Clear per-syscall TIF flags if any are set, but _leave_
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_TIF_SAVE_NVGPRS set in r9 since we haven't dealt with that
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yet. */
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li r11,_TIF_PERSYSCALL_MASK
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addi r12,r12,TI_FLAGS
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3: ldarx r10,0,r12
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andc r10,r10,r11
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stdcx. r10,0,r12
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bne- 3b
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subi r12,r12,TI_FLAGS
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4: bl .save_nvgprs
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/* Anything else left to do? */
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andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SAVE_NVGPRS)
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beq .ret_from_except_lite
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/* Re-enable interrupts */
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mfmsr r10
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ori r10,r10,MSR_EE
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mtmsrd r10,1
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andi. r0,r9,_TIF_SAVE_NVGPRS
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bne save_user_nvgprs
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/* If tracing, re-enable interrupts and do it */
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save_user_nvgprs_cont:
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andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
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beq 5f
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addi r3,r1,STACK_FRAME_OVERHEAD
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bl .do_syscall_trace_leave
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REST_NVGPRS(r1)
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clrrdi r12,r1,THREAD_SHIFT
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/* Disable interrupts again and handle other work if any */
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5: mfmsr r10
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rldicl r10,r10,48,1
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rotldi r10,r10,16
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mtmsrd r10,1
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b .ret_from_except_lite
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/* Save non-volatile GPRs, if not already saved. */
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_GLOBAL(save_nvgprs)
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ld r11,_TRAP(r1)
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andi. r0,r11,1
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beqlr-
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SAVE_NVGPRS(r1)
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clrrdi r0,r11,1
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std r0,_TRAP(r1)
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blr
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save_user_nvgprs:
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ld r10,TI_SIGFRAME(r12)
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andi. r0,r9,_TIF_32BIT
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beq- save_user_nvgprs_64
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/* 32-bit save to userspace */
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.macro savewords start, end
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1: stw \start,4*(\start)(r10)
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.section __ex_table,"a"
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.align 3
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.llong 1b,save_user_nvgprs_fault
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.previous
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.if \end - \start
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savewords "(\start+1)",\end
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.endif
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.endm
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savewords 14,31
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b save_user_nvgprs_cont
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save_user_nvgprs_64:
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/* 64-bit save to userspace */
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.macro savelongs start, end
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1: std \start,8*(\start)(r10)
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.section __ex_table,"a"
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.align 3
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.llong 1b,save_user_nvgprs_fault
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.previous
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.if \end - \start
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savelongs "(\start+1)",\end
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.endif
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.endm
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savelongs 14,31
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b save_user_nvgprs_cont
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save_user_nvgprs_fault:
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li r3,11 /* SIGSEGV */
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ld r4,TI_TASK(r12)
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bl .force_sigsegv
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clrrdi r12,r1,THREAD_SHIFT
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ld r9,TI_FLAGS(r12)
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b save_user_nvgprs_cont
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/*
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* The sigsuspend and rt_sigsuspend system calls can call do_signal
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* and thus put the process into the stopped state where we might
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* want to examine its user state with ptrace. Therefore we need
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* to save all the nonvolatile registers (r14 - r31) before calling
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* the C code. Similarly, fork, vfork and clone need the full
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* register state on the stack so that it can be copied to the child.
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*/
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_GLOBAL(ppc_fork)
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bl .save_nvgprs
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bl .sys_fork
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b syscall_exit
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_GLOBAL(ppc_vfork)
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bl .save_nvgprs
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bl .sys_vfork
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b syscall_exit
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_GLOBAL(ppc_clone)
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bl .save_nvgprs
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bl .sys_clone
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b syscall_exit
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_GLOBAL(ret_from_fork)
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bl .schedule_tail
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REST_NVGPRS(r1)
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li r3,0
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b syscall_exit
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/*
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* This routine switches between two different tasks. The process
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* state of one is saved on its kernel stack. Then the state
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* of the other is restored from its kernel stack. The memory
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* management hardware is updated to the second process's state.
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* Finally, we can return to the second process, via ret_from_except.
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* On entry, r3 points to the THREAD for the current task, r4
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* points to the THREAD for the new task.
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*
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* Note: there are two ways to get to the "going out" portion
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* of this code; either by coming in via the entry (_switch)
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* or via "fork" which must set up an environment equivalent
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* to the "_switch" path. If you change this you'll have to change
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* the fork code also.
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*
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* The code which creates the new task context is in 'copy_thread'
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* in arch/ppc64/kernel/process.c
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*/
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.align 7
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_GLOBAL(_switch)
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mflr r0
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std r0,16(r1)
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stdu r1,-SWITCH_FRAME_SIZE(r1)
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/* r3-r13 are caller saved -- Cort */
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SAVE_8GPRS(14, r1)
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SAVE_10GPRS(22, r1)
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mflr r20 /* Return to switch caller */
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mfmsr r22
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li r0, MSR_FP
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#ifdef CONFIG_ALTIVEC
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BEGIN_FTR_SECTION
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oris r0,r0,MSR_VEC@h /* Disable altivec */
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mfspr r24,SPRN_VRSAVE /* save vrsave register value */
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std r24,THREAD_VRSAVE(r3)
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif /* CONFIG_ALTIVEC */
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and. r0,r0,r22
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beq+ 1f
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andc r22,r22,r0
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mtmsrd r22
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isync
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1: std r20,_NIP(r1)
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mfcr r23
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std r23,_CCR(r1)
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std r1,KSP(r3) /* Set old stack pointer */
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#ifdef CONFIG_SMP
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/* We need a sync somewhere here to make sure that if the
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* previous task gets rescheduled on another CPU, it sees all
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* stores it has performed on this one.
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*/
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sync
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#endif /* CONFIG_SMP */
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addi r6,r4,-THREAD /* Convert THREAD to 'current' */
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std r6,PACACURRENT(r13) /* Set new 'current' */
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ld r8,KSP(r4) /* new stack pointer */
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BEGIN_FTR_SECTION
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clrrdi r6,r8,28 /* get its ESID */
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clrrdi r9,r1,28 /* get current sp ESID */
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clrldi. r0,r6,2 /* is new ESID c00000000? */
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cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
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cror eq,4*cr1+eq,eq
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beq 2f /* if yes, don't slbie it */
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/* Bolt in the new stack SLB entry */
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ld r7,KSP_VSID(r4) /* Get new stack's VSID */
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oris r0,r6,(SLB_ESID_V)@h
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ori r0,r0,(SLB_NUM_BOLTED-1)@l
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slbie r6
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slbie r6 /* Workaround POWER5 < DD2.1 issue */
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slbmte r7,r0
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isync
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2:
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END_FTR_SECTION_IFSET(CPU_FTR_SLB)
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clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
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/* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
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because we don't need to leave the 288-byte ABI gap at the
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top of the kernel stack. */
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addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
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mr r1,r8 /* start using new stack pointer */
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std r7,PACAKSAVE(r13)
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ld r6,_CCR(r1)
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mtcrf 0xFF,r6
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#ifdef CONFIG_ALTIVEC
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BEGIN_FTR_SECTION
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ld r0,THREAD_VRSAVE(r4)
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mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
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END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
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#endif /* CONFIG_ALTIVEC */
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/* r3-r13 are destroyed -- Cort */
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REST_8GPRS(14, r1)
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REST_10GPRS(22, r1)
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/* convert old thread to its task_struct for return value */
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addi r3,r3,-THREAD
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ld r7,_NIP(r1) /* Return to _switch caller in new task */
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mtlr r7
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addi r1,r1,SWITCH_FRAME_SIZE
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blr
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.align 7
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_GLOBAL(ret_from_except)
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ld r11,_TRAP(r1)
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andi. r0,r11,1
|
|
bne .ret_from_except_lite
|
|
REST_NVGPRS(r1)
|
|
|
|
_GLOBAL(ret_from_except_lite)
|
|
/*
|
|
* Disable interrupts so that current_thread_info()->flags
|
|
* can't change between when we test it and when we return
|
|
* from the interrupt.
|
|
*/
|
|
mfmsr r10 /* Get current interrupt state */
|
|
rldicl r9,r10,48,1 /* clear MSR_EE */
|
|
rotldi r9,r9,16
|
|
mtmsrd r9,1 /* Update machine state */
|
|
|
|
#ifdef CONFIG_PREEMPT
|
|
clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
|
|
li r0,_TIF_NEED_RESCHED /* bits to check */
|
|
ld r3,_MSR(r1)
|
|
ld r4,TI_FLAGS(r9)
|
|
/* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
|
|
rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
|
|
and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
|
|
bne do_work
|
|
|
|
#else /* !CONFIG_PREEMPT */
|
|
ld r3,_MSR(r1) /* Returning to user mode? */
|
|
andi. r3,r3,MSR_PR
|
|
beq restore /* if not, just restore regs and return */
|
|
|
|
/* Check current_thread_info()->flags */
|
|
clrrdi r9,r1,THREAD_SHIFT
|
|
ld r4,TI_FLAGS(r9)
|
|
andi. r0,r4,_TIF_USER_WORK_MASK
|
|
bne do_work
|
|
#endif
|
|
|
|
restore:
|
|
#ifdef CONFIG_PPC_ISERIES
|
|
ld r5,SOFTE(r1)
|
|
cmpdi 0,r5,0
|
|
beq 4f
|
|
/* Check for pending interrupts (iSeries) */
|
|
ld r3,PACALPPACA+LPPACAANYINT(r13)
|
|
cmpdi r3,0
|
|
beq+ 4f /* skip do_IRQ if no interrupts */
|
|
|
|
li r3,0
|
|
stb r3,PACAPROCENABLED(r13) /* ensure we are soft-disabled */
|
|
ori r10,r10,MSR_EE
|
|
mtmsrd r10 /* hard-enable again */
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .do_IRQ
|
|
b .ret_from_except_lite /* loop back and handle more */
|
|
|
|
4: stb r5,PACAPROCENABLED(r13)
|
|
#endif
|
|
|
|
ld r3,_MSR(r1)
|
|
andi. r0,r3,MSR_RI
|
|
beq- unrecov_restore
|
|
|
|
andi. r0,r3,MSR_PR
|
|
|
|
/*
|
|
* r13 is our per cpu area, only restore it if we are returning to
|
|
* userspace
|
|
*/
|
|
beq 1f
|
|
REST_GPR(13, r1)
|
|
1:
|
|
ld r3,_CTR(r1)
|
|
ld r0,_LINK(r1)
|
|
mtctr r3
|
|
mtlr r0
|
|
ld r3,_XER(r1)
|
|
mtspr SPRN_XER,r3
|
|
|
|
REST_8GPRS(5, r1)
|
|
|
|
stdcx. r0,0,r1 /* to clear the reservation */
|
|
|
|
mfmsr r0
|
|
li r2, MSR_RI
|
|
andc r0,r0,r2
|
|
mtmsrd r0,1
|
|
|
|
ld r0,_MSR(r1)
|
|
mtspr SPRN_SRR1,r0
|
|
|
|
ld r2,_CCR(r1)
|
|
mtcrf 0xFF,r2
|
|
ld r2,_NIP(r1)
|
|
mtspr SPRN_SRR0,r2
|
|
|
|
ld r0,GPR0(r1)
|
|
ld r2,GPR2(r1)
|
|
ld r3,GPR3(r1)
|
|
ld r4,GPR4(r1)
|
|
ld r1,GPR1(r1)
|
|
|
|
rfid
|
|
b . /* prevent speculative execution */
|
|
|
|
/* Note: this must change if we start using the TIF_NOTIFY_RESUME bit */
|
|
do_work:
|
|
#ifdef CONFIG_PREEMPT
|
|
andi. r0,r3,MSR_PR /* Returning to user mode? */
|
|
bne user_work
|
|
/* Check that preempt_count() == 0 and interrupts are enabled */
|
|
lwz r8,TI_PREEMPT(r9)
|
|
cmpwi cr1,r8,0
|
|
#ifdef CONFIG_PPC_ISERIES
|
|
ld r0,SOFTE(r1)
|
|
cmpdi r0,0
|
|
#else
|
|
andi. r0,r3,MSR_EE
|
|
#endif
|
|
crandc eq,cr1*4+eq,eq
|
|
bne restore
|
|
/* here we are preempting the current task */
|
|
1:
|
|
#ifdef CONFIG_PPC_ISERIES
|
|
li r0,1
|
|
stb r0,PACAPROCENABLED(r13)
|
|
#endif
|
|
ori r10,r10,MSR_EE
|
|
mtmsrd r10,1 /* reenable interrupts */
|
|
bl .preempt_schedule
|
|
mfmsr r10
|
|
clrrdi r9,r1,THREAD_SHIFT
|
|
rldicl r10,r10,48,1 /* disable interrupts again */
|
|
rotldi r10,r10,16
|
|
mtmsrd r10,1
|
|
ld r4,TI_FLAGS(r9)
|
|
andi. r0,r4,_TIF_NEED_RESCHED
|
|
bne 1b
|
|
b restore
|
|
|
|
user_work:
|
|
#endif
|
|
/* Enable interrupts */
|
|
ori r10,r10,MSR_EE
|
|
mtmsrd r10,1
|
|
|
|
andi. r0,r4,_TIF_NEED_RESCHED
|
|
beq 1f
|
|
bl .schedule
|
|
b .ret_from_except_lite
|
|
|
|
1: bl .save_nvgprs
|
|
li r3,0
|
|
addi r4,r1,STACK_FRAME_OVERHEAD
|
|
bl .do_signal
|
|
b .ret_from_except
|
|
|
|
unrecov_restore:
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
bl .unrecoverable_exception
|
|
b unrecov_restore
|
|
|
|
#ifdef CONFIG_PPC_RTAS
|
|
/*
|
|
* On CHRP, the Run-Time Abstraction Services (RTAS) have to be
|
|
* called with the MMU off.
|
|
*
|
|
* In addition, we need to be in 32b mode, at least for now.
|
|
*
|
|
* Note: r3 is an input parameter to rtas, so don't trash it...
|
|
*/
|
|
_GLOBAL(enter_rtas)
|
|
mflr r0
|
|
std r0,16(r1)
|
|
stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
|
|
|
|
/* Because RTAS is running in 32b mode, it clobbers the high order half
|
|
* of all registers that it saves. We therefore save those registers
|
|
* RTAS might touch to the stack. (r0, r3-r13 are caller saved)
|
|
*/
|
|
SAVE_GPR(2, r1) /* Save the TOC */
|
|
SAVE_GPR(13, r1) /* Save paca */
|
|
SAVE_8GPRS(14, r1) /* Save the non-volatiles */
|
|
SAVE_10GPRS(22, r1) /* ditto */
|
|
|
|
mfcr r4
|
|
std r4,_CCR(r1)
|
|
mfctr r5
|
|
std r5,_CTR(r1)
|
|
mfspr r6,SPRN_XER
|
|
std r6,_XER(r1)
|
|
mfdar r7
|
|
std r7,_DAR(r1)
|
|
mfdsisr r8
|
|
std r8,_DSISR(r1)
|
|
mfsrr0 r9
|
|
std r9,_SRR0(r1)
|
|
mfsrr1 r10
|
|
std r10,_SRR1(r1)
|
|
|
|
/* There is no way it is acceptable to get here with interrupts enabled,
|
|
* check it with the asm equivalent of WARN_ON
|
|
*/
|
|
mfmsr r6
|
|
andi. r0,r6,MSR_EE
|
|
1: tdnei r0,0
|
|
.section __bug_table,"a"
|
|
.llong 1b,__LINE__ + 0x1000000, 1f, 2f
|
|
.previous
|
|
.section .rodata,"a"
|
|
1: .asciz __FILE__
|
|
2: .asciz "enter_rtas"
|
|
.previous
|
|
|
|
/* Unfortunately, the stack pointer and the MSR are also clobbered,
|
|
* so they are saved in the PACA which allows us to restore
|
|
* our original state after RTAS returns.
|
|
*/
|
|
std r1,PACAR1(r13)
|
|
std r6,PACASAVEDMSR(r13)
|
|
|
|
/* Setup our real return addr */
|
|
SET_REG_TO_LABEL(r4,.rtas_return_loc)
|
|
SET_REG_TO_CONST(r9,KERNELBASE)
|
|
sub r4,r4,r9
|
|
mtlr r4
|
|
|
|
li r0,0
|
|
ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
|
|
andc r0,r6,r0
|
|
|
|
li r9,1
|
|
rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
|
|
ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP
|
|
andc r6,r0,r9
|
|
ori r6,r6,MSR_RI
|
|
sync /* disable interrupts so SRR0/1 */
|
|
mtmsrd r0 /* don't get trashed */
|
|
|
|
SET_REG_TO_LABEL(r4,rtas)
|
|
ld r5,RTASENTRY(r4) /* get the rtas->entry value */
|
|
ld r4,RTASBASE(r4) /* get the rtas->base value */
|
|
|
|
mtspr SPRN_SRR0,r5
|
|
mtspr SPRN_SRR1,r6
|
|
rfid
|
|
b . /* prevent speculative execution */
|
|
|
|
_STATIC(rtas_return_loc)
|
|
/* relocation is off at this point */
|
|
mfspr r4,SPRN_SPRG3 /* Get PACA */
|
|
SET_REG_TO_CONST(r5, KERNELBASE)
|
|
sub r4,r4,r5 /* RELOC the PACA base pointer */
|
|
|
|
mfmsr r6
|
|
li r0,MSR_RI
|
|
andc r6,r6,r0
|
|
sync
|
|
mtmsrd r6
|
|
|
|
ld r1,PACAR1(r4) /* Restore our SP */
|
|
LOADADDR(r3,.rtas_restore_regs)
|
|
ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
|
|
|
|
mtspr SPRN_SRR0,r3
|
|
mtspr SPRN_SRR1,r4
|
|
rfid
|
|
b . /* prevent speculative execution */
|
|
|
|
_STATIC(rtas_restore_regs)
|
|
/* relocation is on at this point */
|
|
REST_GPR(2, r1) /* Restore the TOC */
|
|
REST_GPR(13, r1) /* Restore paca */
|
|
REST_8GPRS(14, r1) /* Restore the non-volatiles */
|
|
REST_10GPRS(22, r1) /* ditto */
|
|
|
|
mfspr r13,SPRN_SPRG3
|
|
|
|
ld r4,_CCR(r1)
|
|
mtcr r4
|
|
ld r5,_CTR(r1)
|
|
mtctr r5
|
|
ld r6,_XER(r1)
|
|
mtspr SPRN_XER,r6
|
|
ld r7,_DAR(r1)
|
|
mtdar r7
|
|
ld r8,_DSISR(r1)
|
|
mtdsisr r8
|
|
ld r9,_SRR0(r1)
|
|
mtsrr0 r9
|
|
ld r10,_SRR1(r1)
|
|
mtsrr1 r10
|
|
|
|
addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
|
|
ld r0,16(r1) /* get return address */
|
|
|
|
mtlr r0
|
|
blr /* return to caller */
|
|
|
|
#endif /* CONFIG_PPC_RTAS */
|
|
|
|
#ifdef CONFIG_PPC_MULTIPLATFORM
|
|
|
|
_GLOBAL(enter_prom)
|
|
mflr r0
|
|
std r0,16(r1)
|
|
stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
|
|
|
|
/* Because PROM is running in 32b mode, it clobbers the high order half
|
|
* of all registers that it saves. We therefore save those registers
|
|
* PROM might touch to the stack. (r0, r3-r13 are caller saved)
|
|
*/
|
|
SAVE_8GPRS(2, r1)
|
|
SAVE_GPR(13, r1)
|
|
SAVE_8GPRS(14, r1)
|
|
SAVE_10GPRS(22, r1)
|
|
mfcr r4
|
|
std r4,_CCR(r1)
|
|
mfctr r5
|
|
std r5,_CTR(r1)
|
|
mfspr r6,SPRN_XER
|
|
std r6,_XER(r1)
|
|
mfdar r7
|
|
std r7,_DAR(r1)
|
|
mfdsisr r8
|
|
std r8,_DSISR(r1)
|
|
mfsrr0 r9
|
|
std r9,_SRR0(r1)
|
|
mfsrr1 r10
|
|
std r10,_SRR1(r1)
|
|
mfmsr r11
|
|
std r11,_MSR(r1)
|
|
|
|
/* Get the PROM entrypoint */
|
|
ld r0,GPR4(r1)
|
|
mtlr r0
|
|
|
|
/* Switch MSR to 32 bits mode
|
|
*/
|
|
mfmsr r11
|
|
li r12,1
|
|
rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
|
|
andc r11,r11,r12
|
|
li r12,1
|
|
rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
|
|
andc r11,r11,r12
|
|
mtmsrd r11
|
|
isync
|
|
|
|
/* Restore arguments & enter PROM here... */
|
|
ld r3,GPR3(r1)
|
|
blrl
|
|
|
|
/* Just make sure that r1 top 32 bits didn't get
|
|
* corrupt by OF
|
|
*/
|
|
rldicl r1,r1,0,32
|
|
|
|
/* Restore the MSR (back to 64 bits) */
|
|
ld r0,_MSR(r1)
|
|
mtmsrd r0
|
|
isync
|
|
|
|
/* Restore other registers */
|
|
REST_GPR(2, r1)
|
|
REST_GPR(13, r1)
|
|
REST_8GPRS(14, r1)
|
|
REST_10GPRS(22, r1)
|
|
ld r4,_CCR(r1)
|
|
mtcr r4
|
|
ld r5,_CTR(r1)
|
|
mtctr r5
|
|
ld r6,_XER(r1)
|
|
mtspr SPRN_XER,r6
|
|
ld r7,_DAR(r1)
|
|
mtdar r7
|
|
ld r8,_DSISR(r1)
|
|
mtdsisr r8
|
|
ld r9,_SRR0(r1)
|
|
mtsrr0 r9
|
|
ld r10,_SRR1(r1)
|
|
mtsrr1 r10
|
|
|
|
addi r1,r1,PROM_FRAME_SIZE
|
|
ld r0,16(r1)
|
|
mtlr r0
|
|
blr
|
|
|
|
#endif /* CONFIG_PPC_MULTIPLATFORM */
|