Alexander Shishkin 92ca7da4bd perf/x86/intel: Fix PT PMI handling ... Commit: ccbebba4c6 ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") skips the PT/LBR exclusivity check on CPUs where PT and LBRs coexist, but also inadvertently skips the active_events bump for PT in that case, which is a bug. If there aren't any hardware events at the same time as PT, the PMI handler will ignore PT PMIs, as active_events reads zero in that case, resulting in the "Uhhuh" spurious NMI warning and PT data loss. Fix this by always increasing active_events for PT events. Fixes: ccbebba4c6 ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it") Reported-by: Vitaly Slobodskoy <vitaly.slobodskoy@intel.com> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Alexey Budankov <alexey.budankov@linux.intel.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Link: https://lkml.kernel.org/r/20191210105101.77210-1-alexander.shishkin@linux.intel.com		2019-12-17 13:32:46 +01:00
..
amd	perf/x86/amd: Remove set but not used variable 'active'	2019-11-11 08:31:55 +01:00
intel	perf/x86/intel/bts: Fix the use of page_private()	2019-12-17 13:32:46 +01:00
core.c	perf/x86/intel: Fix PT PMI handling	2019-12-17 13:32:46 +01:00
Kconfig
Makefile
msr.c	perf/x86/msr: Add Tiger Lake CPU support	2019-10-12 15:13:09 +02:00
perf_event.h	perf/x86/intel: Implement LBR callstack context synchronization	2019-10-28 12:51:01 +01:00
probe.c
probe.h