forked from luck/tmp_suning_uos_patched
186 lines
6.2 KiB
C
186 lines
6.2 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* PCI specific definitions
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*
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* Author: source@mvista.com
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef __PNX8550_PCI_H
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#define __PNX8550_PCI_H
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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#define PCI_CMD_IOR 0x20
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#define PCI_CMD_IOW 0x30
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#define PCI_CMD_CONFIG_READ 0xa0
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#define PCI_CMD_CONFIG_WRITE 0xb0
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#define PCI_IO_TIMEOUT 1000
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#define PCI_IO_RETRY 5
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/* Timeout for IO and CFG accesses.
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This is in 1/1024 th of a jiffie(=10ms)
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i.e. approx 10us */
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#define PCI_IO_JIFFIES_TIMEOUT 40
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#define PCI_IO_JIFFIES_SHIFT 10
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#define PCI_BYTE_ENABLE_MASK 0x0000000f
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#define PCI_CFG_BUS_SHIFT 16
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#define PCI_CFG_FUNC_SHIFT 8
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#define PCI_CFG_REG_SHIFT 2
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#define PCI_BASE 0x1be00000
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#define PCI_SETUP 0x00040010
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#define PCI_DIS_REQGNT (1<<30)
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#define PCI_DIS_REQGNTA (1<<29)
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#define PCI_DIS_REQGNTB (1<<28)
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#define PCI_D2_SUPPORT (1<<27)
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#define PCI_D1_SUPPORT (1<<26)
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#define PCI_EN_TA (1<<24)
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#define PCI_EN_PCI2MMI (1<<23)
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#define PCI_EN_XIO (1<<22)
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#define PCI_BASE18_PREF (1<<21)
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#define SIZE_16M 0x3
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#define SIZE_32M 0x4
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#define SIZE_64M 0x5
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#define SIZE_128M 0x6
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#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
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#define PCI_SETUP_BASE18_EN (1<<17)
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#define PCI_SETUP_BASE14_PREF (1<<16)
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#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
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#define PCI_SETUP_BASE14_EN (1<<11)
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#define PCI_SETUP_BASE10_PREF (1<<10)
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#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
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#define PCI_SETUP_CFGMANAGE_EN (1<<1)
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#define PCI_SETUP_PCIARB_EN (1<<0)
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#define PCI_CTRL 0x040014
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#define PCI_SWPB_DCS_PCI (1<<16)
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#define PCI_SWPB_PCI_PCI (1<<15)
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#define PCI_SWPB_PCI_DCS (1<<14)
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#define PCI_REG_WR_POST (1<<13)
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#define PCI_XIO_WR_POST (1<<12)
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#define PCI_PCI2_WR_POST (1<<13)
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#define PCI_PCI1_WR_POST (1<<12)
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#define PCI_SERR_SEEN (1<<11)
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#define PCI_B10_SPEC_RD (1<<6)
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#define PCI_B14_SPEC_RD (1<<5)
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#define PCI_B18_SPEC_RD (1<<4)
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#define PCI_B10_NOSUBWORD (1<<3)
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#define PCI_B14_NOSUBWORD (1<<2)
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#define PCI_B18_NOSUBWORD (1<<1)
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#define PCI_RETRY_TMREN (1<<0)
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#define PCI_BASE1_LO 0x040018
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#define PCI_BASE1_HI 0x04001C
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#define PCI_BASE2_LO 0x040020
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#define PCI_BASE2_HI 0x040024
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#define PCI_RDLIFETIM 0x040028
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#define PCI_GPPM_ADDR 0x04002C
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#define PCI_GPPM_WDAT 0x040030
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#define PCI_GPPM_RDAT 0x040034
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#define PCI_GPPM_CTRL 0x040038
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#define GPPM_DONE (1<<10)
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#define INIT_PCI_CYCLE (1<<9)
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#define GPPM_CMD(X) (((X)&0xf)<<4)
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#define GPPM_BYTEEN(X) ((X)&0xf)
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#define PCI_UNLOCKREG 0x04003C
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#define UNLOCK_SSID(X) (((X)&0xff)<<8)
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#define UNLOCK_SETUP(X) (((X)&0xff)<<0)
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#define UNLOCK_MAGIC 0xCA
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#define PCI_DEV_VEND_ID 0x040040
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#define DEVICE_ID(X) (((X)>>16)&0xffff)
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#define VENDOR_ID(X) (((X)&0xffff))
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#define PCI_CFG_CMDSTAT 0x040044
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#define PCI_CFG_STATUS(X) (((X)>>16)&0xffff)
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#define PCI_CFG_COMMAND(X) ((X)&0xffff)
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#define PCI_CLASS_REV 0x040048
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#define PCI_CLASSCODE(X) (((X)>>8)&0xffffff)
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#define PCI_REVID(X) ((X)&0xff)
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#define PCI_LAT_TMR 0x04004c
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#define PCI_BASE10 0x040050
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#define PCI_BASE14 0x040054
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#define PCI_BASE18 0x040058
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#define PCI_SUBSYS_ID 0x04006c
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#define PCI_CAP_PTR 0x040074
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#define PCI_CFG_MISC 0x04007c
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#define PCI_PMC 0x040080
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#define PCI_PWR_STATE 0x040084
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#define PCI_IO 0x040088
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#define PCI_SLVTUNING 0x04008C
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#define PCI_DMATUNING 0x040090
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#define PCI_DMAEADDR 0x040800
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#define PCI_DMAIADDR 0x040804
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#define PCI_DMALEN 0x040808
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#define PCI_DMACTRL 0x04080C
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#define PCI_XIOCTRL 0x040810
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#define PCI_SEL0PROF 0x040814
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#define PCI_SEL1PROF 0x040818
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#define PCI_SEL2PROF 0x04081C
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#define PCI_GPXIOADDR 0x040820
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#define PCI_NANDCTRLS 0x400830
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#define PCI_SEL3PROF 0x040834
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#define PCI_SEL4PROF 0x040838
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#define PCI_GPXIO_STAT 0x040FB0
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#define PCI_GPXIO_IMASK 0x040FB4
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#define PCI_GPXIO_ICLR 0x040FB8
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#define PCI_GPXIO_ISET 0x040FBC
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#define PCI_GPPM_STATUS 0x040FC0
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#define GPPM_DONE (1<<10)
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#define GPPM_ERR (1<<9)
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#define GPPM_MPAR_ERR (1<<8)
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#define GPPM_PAR_ERR (1<<7)
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#define GPPM_R_MABORT (1<<2)
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#define GPPM_R_TABORT (1<<1)
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#define PCI_GPPM_IMASK 0x040FC4
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#define PCI_GPPM_ICLR 0x040FC8
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#define PCI_GPPM_ISET 0x040FCC
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#define PCI_DMA_STATUS 0x040FD0
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#define PCI_DMA_IMASK 0x040FD4
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#define PCI_DMA_ICLR 0x040FD8
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#define PCI_DMA_ISET 0x040FDC
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#define PCI_ISTATUS 0x040FE0
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#define PCI_IMASK 0x040FE4
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#define PCI_ICLR 0x040FE8
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#define PCI_ISET 0x040FEC
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#define PCI_MOD_ID 0x040FFC
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/*
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* PCI configuration cycle AD bus definition
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*/
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/* Type 0 */
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#define PCI_CFG_TYPE0_REG_SHF 0
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#define PCI_CFG_TYPE0_FUNC_SHF 8
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/* Type 1 */
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#define PCI_CFG_TYPE1_REG_SHF 0
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#define PCI_CFG_TYPE1_FUNC_SHF 8
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#define PCI_CFG_TYPE1_DEV_SHF 11
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#define PCI_CFG_TYPE1_BUS_SHF 16
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/*
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* Ethernet device DP83816 definition
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*/
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#define DP83816_IRQ_ETHER 66
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#endif
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