forked from luck/tmp_suning_uos_patched
6b04e0d99d
One of the clock domains was missing from the auto-generated file. It has been added here. Signed-off-by: Abhijit Pagare <abhijitpagare@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
251 lines
8.1 KiB
C
251 lines
8.1 KiB
C
/*
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* OMAP4 Clock domains framework
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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* Copyright (C) 2009 Nokia Corporation
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*
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* Abhijit Pagare (abhijitpagare@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* To-Do List
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* -> Populate the Sleep/Wakeup dependencies for the domains
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS44XX_H
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#include <plat/clockdomain.h>
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#if defined(CONFIG_ARCH_OMAP4)
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static struct clockdomain l4_cefuse_44xx_clkdm = {
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.name = "l4_cefuse_clkdm",
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.pwrdm = { .name = "cefuse_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_cfg_44xx_clkdm = {
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.name = "l4_cfg_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain tesla_44xx_clkdm = {
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.name = "tesla_clkdm",
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.pwrdm = { .name = "tesla_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_gfx_44xx_clkdm = {
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.name = "l3_gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain ivahd_44xx_clkdm = {
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.name = "ivahd_clkdm",
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.pwrdm = { .name = "ivahd_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_secure_44xx_clkdm = {
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.name = "l4_secure_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_per_44xx_clkdm = {
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.name = "l4_per_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain abe_44xx_clkdm = {
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.name = "abe_clkdm",
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.pwrdm = { .name = "abe_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_instr_44xx_clkdm = {
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.name = "l3_instr_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_init_44xx_clkdm = {
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.name = "l3_init_clkdm",
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.pwrdm = { .name = "l3init_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpuss_44xx_clkdm = {
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.name = "mpuss_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpu0_44xx_clkdm = {
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.name = "mpu0_clkdm",
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.pwrdm = { .name = "cpu0_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_PDA_CPU0_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpu1_44xx_clkdm = {
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.name = "mpu1_clkdm",
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.pwrdm = { .name = "cpu1_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_PDA_CPU1_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_emif_44xx_clkdm = {
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.name = "l3_emif_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_ao_44xx_clkdm = {
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.name = "l4_ao_clkdm",
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.pwrdm = { .name = "always_on_core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain ducati_44xx_clkdm = {
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.name = "ducati_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_2_44xx_clkdm = {
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.name = "l3_2_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_1_44xx_clkdm = {
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.name = "l3_1_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_d2d_44xx_clkdm = {
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.name = "l3_d2d_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain iss_44xx_clkdm = {
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.name = "iss_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_dss_44xx_clkdm = {
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.name = "l3_dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_wkup_44xx_clkdm = {
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.name = "l4_wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain emu_sys_44xx_clkdm = {
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.name = "emu_sys_clkdm",
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.pwrdm = { .name = "emu_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_dma_44xx_clkdm = {
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.name = "l3_dma_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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#endif
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#endif
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