forked from luck/tmp_suning_uos_patched
0ae2d26ffe
Avoid un-intended DCTI Couples. Use of DCTI couples is deprecated. Also address the "Programming Note" for optimal performance. Here is the complete text from Oracle SPARC Architecture Specs. 6.3.4.7 DCTI Couples "A delayed control transfer instruction (DCTI) in the delay slot of another DCTI is referred to as a “DCTI couple”. The use of DCTI couples is deprecated in the Oracle SPARC Architecture; no new software should place a DCTI in the delay slot of another DCTI, because on future Oracle SPARC Architecture implementations DCTI couples may execute either slowly or differently than the programmer assumes it will. SPARC V8 and SPARC V9 Compatibility Note The SPARC V8 architecture left behavior undefined for a DCTI couple. The SPARC V9 architecture defined behavior in that case, but as of UltraSPARC Architecture 2005, use of DCTI couples was deprecated. Software should not expect high performance from DCTI couples, and performance of DCTI couples should be expected to decline further in future processors. Programming Note As noted in TABLE 6-5 on page 115, an annulled branch-always (branch-always with a = 1) instruction is not architecturally a DCTI. However, since not all implementations make that distinction, for optimal performance, a DCTI should not be placed in the instruction word immediately following an annulled branch-always instruction (BA,A or BPA,A)." Signed-off-by: Babu Moger <babu.moger@oracle.com> Reviewed-by: Rob Gardner <rob.gardner@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
160 lines
3.9 KiB
ArmAsm
160 lines
3.9 KiB
ArmAsm
/* winfixup.S: Handle cases where user stack pointer is found to be bogus.
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*
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* Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
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*/
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#include <asm/asi.h>
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#include <asm/head.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/spitfire.h>
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#include <asm/thread_info.h>
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.text
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/* It used to be the case that these register window fault
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* handlers could run via the save and restore instructions
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* done by the trap entry and exit code. They now do the
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* window spill/fill by hand, so that case no longer can occur.
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*/
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.align 32
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fill_fixup:
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TRAP_LOAD_THREAD_REG(%g6, %g1)
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rdpr %tstate, %g1
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and %g1, TSTATE_CWP, %g1
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or %g4, FAULT_CODE_WINFIXUP, %g4
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_sparc64_fault
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Be very careful about usage of the trap globals here.
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* You cannot touch %g5 as that has the fault information.
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*/
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spill_fixup:
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spill_fixup_mna:
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spill_fixup_dax:
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TRAP_LOAD_THREAD_REG(%g6, %g1)
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ldx [%g6 + TI_FLAGS], %g1
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andcc %sp, 0x1, %g0
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movne %icc, 0, %g1
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andcc %g1, _TIF_32BIT, %g0
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ldub [%g6 + TI_WSAVED], %g1
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sll %g1, 3, %g3
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add %g6, %g3, %g3
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stx %sp, [%g3 + TI_RWIN_SPTRS]
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sll %g1, 7, %g3
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bne,pt %xcc, 1f
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add %g6, %g3, %g3
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stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
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stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
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stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
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stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
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stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
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stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
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stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
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stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
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stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
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stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
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stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
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stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
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stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
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stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
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ba,pt %xcc, 2f
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stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
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1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
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stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
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stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
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stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
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stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
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stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
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stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
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stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
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stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
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stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
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stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
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stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
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stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
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stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
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stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
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2: add %g1, 1, %g1
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stb %g1, [%g6 + TI_WSAVED]
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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saved
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be,pn %xcc, 1f
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and %g1, TSTATE_CWP, %g1
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retry
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1: mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_sparc64_fault
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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winfix_mna:
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andn %g3, 0x7f, %g3
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add %g3, 0x78, %g3
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wrpr %g3, %tnpc
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done
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fill_fixup_mna:
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rdpr %tstate, %g1
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and %g1, TSTATE_CWP, %g1
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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sethi %hi(tlb_type), %g1
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lduw [%g1 + %lo(tlb_type)], %g1
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cmp %g1, 3
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bne,pt %icc, 1f
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add %sp, PTREGS_OFF, %o0
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mov %l4, %o2
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call sun4v_do_mna
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mov %l5, %o1
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ba,a,pt %xcc, rtrap
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1: mov %l4, %o1
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mov %l5, %o2
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call mem_address_unaligned
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nop
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ba,a,pt %xcc, rtrap
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winfix_dax:
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andn %g3, 0x7f, %g3
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add %g3, 0x74, %g3
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wrpr %g3, %tnpc
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done
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fill_fixup_dax:
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rdpr %tstate, %g1
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and %g1, TSTATE_CWP, %g1
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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sethi %hi(tlb_type), %g1
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mov %l4, %o1
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lduw [%g1 + %lo(tlb_type)], %g1
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mov %l5, %o2
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cmp %g1, 3
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bne,pt %icc, 1f
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add %sp, PTREGS_OFF, %o0
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call sun4v_data_access_exception
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nop
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ba,a,pt %xcc, rtrap
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nop
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1: call spitfire_data_access_exception
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nop
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ba,a,pt %xcc, rtrap
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nop
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