forked from luck/tmp_suning_uos_patched
45ed285b54
SH7780 has a speculative execution mode where it can speculatively perform an instruction fetch for subroutine returns, this allows it to be enabled. There are some various pitfalls associated with this mode, so it's left as depending on CONFIG_EXPERIMENTAL and not enabled by default. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
284 lines
6.7 KiB
C
284 lines
6.7 KiB
C
/*
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* arch/sh/kernel/cpu/init.c
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*
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* CPU init code
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*
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* Copyright (C) 2002 - 2007 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#include <asm/page.h>
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#include <asm/system.h>
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#include <asm/cacheflush.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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extern void detect_cpu_and_cache_system(void);
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/*
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* Generic wrapper for command line arguments to disable on-chip
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* peripherals (nofpu, nodsp, and so forth).
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*/
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#define onchip_setup(x) \
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static int x##_disabled __initdata = 0; \
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\
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static int __init x##_setup(char *opts) \
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{ \
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x##_disabled = 1; \
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return 1; \
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} \
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__setup("no" __stringify(x), x##_setup);
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onchip_setup(fpu);
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onchip_setup(dsp);
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#ifdef CONFIG_SPECULATIVE_EXECUTION
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#define CPUOPM 0xff2f0000
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#define CPUOPM_RABD (1 << 5)
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static void __init speculative_execution_init(void)
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{
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/* Clear RABD */
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ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
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/* Flush the update */
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(void)ctrl_inl(CPUOPM);
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ctrl_barrier();
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}
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#else
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#define speculative_execution_init() do { } while (0)
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#endif
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/*
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* Generic first-level cache init
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*/
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static void __init cache_init(void)
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{
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unsigned long ccr, flags;
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/* First setup the rest of the I-cache info */
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current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
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current_cpu_data.icache.linesz;
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current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
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current_cpu_data.icache.linesz;
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/* And the D-cache too */
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current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
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current_cpu_data.dcache.linesz;
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
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current_cpu_data.dcache.linesz;
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jump_to_P2();
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ccr = ctrl_inl(CCR);
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/*
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* At this point we don't know whether the cache is enabled or not - a
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* bootloader may have enabled it. There are at least 2 things that
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* could be dirty in the cache at this point:
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* 1. kernel command line set up by boot loader
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* 2. spilled registers from the prolog of this function
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* => before re-initialising the cache, we must do a purge of the whole
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* cache out to memory for safety. As long as nothing is spilled
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* during the loop to lines that have already been done, this is safe.
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* - RPC
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*/
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if (ccr & CCR_CACHE_ENABLE) {
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unsigned long ways, waysize, addrstart;
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waysize = current_cpu_data.dcache.sets;
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#ifdef CCR_CACHE_ORA
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/*
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* If the OC is already in RAM mode, we only have
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* half of the entries to flush..
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*/
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if (ccr & CCR_CACHE_ORA)
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waysize >>= 1;
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#endif
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waysize <<= current_cpu_data.dcache.entry_shift;
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#ifdef CCR_CACHE_EMODE
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/* If EMODE is not set, we only have 1 way to flush. */
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if (!(ccr & CCR_CACHE_EMODE))
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ways = 1;
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else
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#endif
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ways = current_cpu_data.dcache.ways;
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addrstart = CACHE_OC_ADDRESS_ARRAY;
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do {
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unsigned long addr;
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for (addr = addrstart;
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addr < addrstart + waysize;
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addr += current_cpu_data.dcache.linesz)
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ctrl_outl(0, addr);
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addrstart += current_cpu_data.dcache.way_incr;
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} while (--ways);
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}
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/*
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* Default CCR values .. enable the caches
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* and invalidate them immediately..
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*/
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flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
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#ifdef CCR_CACHE_EMODE
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/* Force EMODE if possible */
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if (current_cpu_data.dcache.ways > 1)
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flags |= CCR_CACHE_EMODE;
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else
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flags &= ~CCR_CACHE_EMODE;
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#endif
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#ifdef CONFIG_SH_WRITETHROUGH
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/* Turn on Write-through caching */
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flags |= CCR_CACHE_WT;
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#else
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/* .. or default to Write-back */
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flags |= CCR_CACHE_CB;
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#endif
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#ifdef CONFIG_SH_OCRAM
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/* Turn on OCRAM -- halve the OC */
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flags |= CCR_CACHE_ORA;
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current_cpu_data.dcache.sets >>= 1;
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current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
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current_cpu_data.dcache.linesz;
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#endif
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ctrl_outl(flags, CCR);
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back_to_P1();
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}
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#ifdef CONFIG_SH_DSP
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static void __init release_dsp(void)
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{
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unsigned long sr;
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/* Clear SR.DSP bit */
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__asm__ __volatile__ (
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"stc\tsr, %0\n\t"
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"and\t%1, %0\n\t"
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"ldc\t%0, sr\n\t"
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: "=&r" (sr)
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: "r" (~SR_DSP)
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);
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}
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static void __init dsp_init(void)
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{
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unsigned long sr;
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/*
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* Set the SR.DSP bit, wait for one instruction, and then read
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* back the SR value.
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*/
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__asm__ __volatile__ (
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"stc\tsr, %0\n\t"
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"or\t%1, %0\n\t"
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"ldc\t%0, sr\n\t"
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"nop\n\t"
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"stc\tsr, %0\n\t"
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: "=&r" (sr)
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: "r" (SR_DSP)
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);
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/* If the DSP bit is still set, this CPU has a DSP */
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if (sr & SR_DSP)
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current_cpu_data.flags |= CPU_HAS_DSP;
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/* Now that we've determined the DSP status, clear the DSP bit. */
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release_dsp();
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}
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#endif /* CONFIG_SH_DSP */
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/**
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* sh_cpu_init
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*
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* This is our initial entry point for each CPU, and is invoked on the boot
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* CPU prior to calling start_kernel(). For SMP, a combination of this and
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* start_secondary() will bring up each processor to a ready state prior
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* to hand forking the idle loop.
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*
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* We do all of the basic processor init here, including setting up the
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* caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
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* hit (and subsequently platform_setup()) things like determining the
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* CPU subtype and initial configuration will all be done.
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*
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* Each processor family is still responsible for doing its own probing
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* and cache configuration in detect_cpu_and_cache_system().
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*/
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asmlinkage void __init sh_cpu_init(void)
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{
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/* First, probe the CPU */
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detect_cpu_and_cache_system();
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if (current_cpu_data.type == CPU_SH_NONE)
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panic("Unknown CPU");
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/* Init the cache */
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cache_init();
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shm_align_mask = max_t(unsigned long,
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current_cpu_data.dcache.way_size - 1,
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PAGE_SIZE - 1);
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/* Disable the FPU */
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if (fpu_disabled) {
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printk("FPU Disabled\n");
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current_cpu_data.flags &= ~CPU_HAS_FPU;
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disable_fpu();
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}
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/* FPU initialization */
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if ((current_cpu_data.flags & CPU_HAS_FPU)) {
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clear_thread_flag(TIF_USEDFPU);
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clear_used_math();
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}
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/*
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* Initialize the per-CPU ASID cache very early, since the
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* TLB flushing routines depend on this being setup.
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*/
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current_cpu_data.asid_cache = NO_CONTEXT;
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#ifdef CONFIG_SH_DSP
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/* Probe for DSP */
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dsp_init();
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/* Disable the DSP */
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if (dsp_disabled) {
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printk("DSP Disabled\n");
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current_cpu_data.flags &= ~CPU_HAS_DSP;
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release_dsp();
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}
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#endif
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#ifdef CONFIG_UBC_WAKEUP
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/*
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* Some brain-damaged loaders decided it would be a good idea to put
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* the UBC to sleep. This causes some issues when it comes to things
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* like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So ..
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* we wake it up and hope that all is well.
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*/
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ubc_wakeup();
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#endif
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speculative_execution_init();
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}
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