forked from luck/tmp_suning_uos_patched
69a517b247
The sp804 binding is already in use by several platforms. This adds missing documentation for the binding and also extends the binding to handle some additional possible interrupt configurations. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
30 lines
1.1 KiB
Plaintext
30 lines
1.1 KiB
Plaintext
ARM sp804 Dual Timers
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Required properties:
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- compatible: Should be "arm,sp804" & "arm,primecell"
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- interrupts: Should contain the list of Dual Timer interrupts. This is the
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interrupt for timer 1 and timer 2. In the case of a single entry, it is
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the combined interrupt or if "arm,sp804-has-irq" is present that
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specifies which timer interrupt is connected.
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- reg: Should contain location and length for dual timer register.
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- clocks: clocks driving the dual timer hardware. This list should be 1 or 3
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clocks. With 3 clocks, the order is timer0 clock, timer1 clock,
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apb_pclk. A single clock can also be specified if the same clock is
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used for all clock inputs.
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Optional properties:
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- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this
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specifies if the irq connection is for timer 1 or timer 2. A value of 1
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or 2 should be used.
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Example:
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timer0: timer@fc800000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0xfc800000 0x1000>;
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interrupts = <0 0 4>, <0 1 4>;
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clocks = <&timclk1 &timclk2 &pclk>;
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clock-names = "timer1", "timer2", "apb_pclk";
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};
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