forked from luck/tmp_suning_uos_patched
91e0806332
Define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE also for processor configurations that don't have cache-aliasing. Signed-off-by: Chris Zankel <chris@zankel.net>
257 lines
7.1 KiB
C
257 lines
7.1 KiB
C
/*
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* include/asm-xtensa/cacheflush.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) 2001 - 2007 Tensilica Inc.
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*/
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#ifndef _XTENSA_CACHEFLUSH_H
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#define _XTENSA_CACHEFLUSH_H
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#ifdef __KERNEL__
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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/*
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* Lo-level routines for cache flushing.
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*
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* invalidate data or instruction cache:
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*
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* __invalidate_icache_all()
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* __invalidate_icache_page(adr)
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* __invalidate_dcache_page(adr)
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* __invalidate_icache_range(from,size)
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* __invalidate_dcache_range(from,size)
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*
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* flush data cache:
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*
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* __flush_dcache_page(adr)
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*
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* flush and invalidate data cache:
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*
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* __flush_invalidate_dcache_all()
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* __flush_invalidate_dcache_page(adr)
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* __flush_invalidate_dcache_range(from,size)
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*
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* specials for cache aliasing:
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*
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* __flush_invalidate_dcache_page_alias(vaddr,paddr)
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* __invalidate_icache_page_alias(vaddr,paddr)
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*/
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extern void __invalidate_dcache_all(void);
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extern void __invalidate_icache_all(void);
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extern void __invalidate_dcache_page(unsigned long);
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extern void __invalidate_icache_page(unsigned long);
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extern void __invalidate_icache_range(unsigned long, unsigned long);
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extern void __invalidate_dcache_range(unsigned long, unsigned long);
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#if XCHAL_DCACHE_IS_WRITEBACK
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extern void __flush_invalidate_dcache_all(void);
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extern void __flush_dcache_page(unsigned long);
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extern void __flush_dcache_range(unsigned long, unsigned long);
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extern void __flush_invalidate_dcache_page(unsigned long);
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extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
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#else
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# define __flush_dcache_range(p,s) do { } while(0)
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# define __flush_dcache_page(p) do { } while(0)
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# define __flush_invalidate_dcache_page(p) __invalidate_dcache_page(p)
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# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s)
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#endif
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#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
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#else
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static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
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unsigned long phys) { }
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#endif
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#if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE)
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extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
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#else
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static inline void __invalidate_icache_page_alias(unsigned long virt,
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unsigned long phys) { }
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#endif
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/*
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* We have physically tagged caches - nothing to do here -
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* unless we have cache aliasing.
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*
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* Pages can get remapped. Because this might change the 'color' of that page,
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* we have to flush the cache before the PTE is changed.
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* (see also Documentation/cachetlb.txt)
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*/
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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#define flush_cache_all() \
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do { \
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__flush_invalidate_dcache_all(); \
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__invalidate_icache_all(); \
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} while (0)
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#define flush_cache_mm(mm) flush_cache_all()
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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#define flush_cache_vmap(start,end) flush_cache_all()
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#define flush_cache_vunmap(start,end) flush_cache_all()
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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extern void flush_dcache_page(struct page*);
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extern void flush_cache_range(struct vm_area_struct*, ulong, ulong);
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extern void flush_cache_page(struct vm_area_struct*, unsigned long, unsigned long);
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#else
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#define flush_cache_all() do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_dup_mm(mm) do { } while (0)
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#define flush_cache_vmap(start,end) do { } while (0)
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#define flush_cache_vunmap(start,end) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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#define flush_dcache_page(page) do { } while (0)
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#define flush_cache_page(vma,addr,pfn) do { } while (0)
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#define flush_cache_range(vma,start,end) do { } while (0)
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#endif
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/* Ensure consistency between data and instruction cache. */
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#define flush_icache_range(start,end) \
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do { \
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__flush_dcache_range(start, (end) - (start)); \
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__invalidate_icache_range(start,(end) - (start)); \
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} while (0)
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/* This is not required, see Documentation/cachetlb.txt */
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#define flush_icache_page(vma,page) do { } while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#if (DCACHE_WAY_SIZE > PAGE_SIZE)
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extern void copy_to_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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extern void copy_from_user_page(struct vm_area_struct*, struct page*,
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unsigned long, void*, const void*, unsigned long);
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#else
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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memcpy(dst, src, len); \
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__flush_dcache_range((unsigned long) dst, len); \
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__invalidate_icache_range((unsigned long) dst, len); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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memcpy(dst, src, len)
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#endif
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#define XTENSA_CACHEBLK_LOG2 29
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#define XTENSA_CACHEBLK_SIZE (1 << XTENSA_CACHEBLK_LOG2)
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#define XTENSA_CACHEBLK_MASK (7 << XTENSA_CACHEBLK_LOG2)
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#if XCHAL_HAVE_CACHEATTR
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static inline u32 xtensa_get_cacheattr(void)
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{
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u32 r;
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asm volatile(" rsr %0, CACHEATTR" : "=a"(r));
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return r;
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}
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static inline u32 xtensa_get_dtlb1(u32 addr)
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{
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u32 r = addr & XTENSA_CACHEBLK_MASK;
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return r | ((xtensa_get_cacheattr() >> (r >> (XTENSA_CACHEBLK_LOG2-2)))
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& 0xF);
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}
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#else
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static inline u32 xtensa_get_dtlb1(u32 addr)
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{
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u32 r;
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asm volatile(" rdtlb1 %0, %1" : "=a"(r) : "a"(addr));
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asm volatile(" dsync");
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return r;
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}
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static inline u32 xtensa_get_cacheattr(void)
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{
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u32 r = 0;
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u32 a = 0;
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do {
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a -= XTENSA_CACHEBLK_SIZE;
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r = (r << 4) | (xtensa_get_dtlb1(a) & 0xF);
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} while (a);
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return r;
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}
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#endif
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static inline int xtensa_need_flush_dma_source(u32 addr)
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{
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return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) >= 4;
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}
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static inline int xtensa_need_invalidate_dma_destination(u32 addr)
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{
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return (xtensa_get_dtlb1(addr) & ((1 << XCHAL_CA_BITS) - 1)) != 2;
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}
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static inline void flush_dcache_unaligned(u32 addr, u32 size)
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{
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u32 cnt;
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if (size) {
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cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
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+ XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
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while (cnt--) {
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asm volatile(" dhwb %0, 0" : : "a"(addr));
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addr += XCHAL_DCACHE_LINESIZE;
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}
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asm volatile(" dsync");
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}
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}
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static inline void invalidate_dcache_unaligned(u32 addr, u32 size)
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{
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int cnt;
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if (size) {
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asm volatile(" dhwbi %0, 0 ;" : : "a"(addr));
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cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
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- XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
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while (cnt-- > 0) {
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asm volatile(" dhi %0, %1" : : "a"(addr),
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"n"(XCHAL_DCACHE_LINESIZE));
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addr += XCHAL_DCACHE_LINESIZE;
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}
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asm volatile(" dhwbi %0, %1" : : "a"(addr),
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"n"(XCHAL_DCACHE_LINESIZE));
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asm volatile(" dsync");
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}
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}
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static inline void flush_invalidate_dcache_unaligned(u32 addr, u32 size)
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{
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u32 cnt;
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if (size) {
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cnt = (size + ((XCHAL_DCACHE_LINESIZE - 1) & addr)
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+ XCHAL_DCACHE_LINESIZE - 1) / XCHAL_DCACHE_LINESIZE;
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while (cnt--) {
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asm volatile(" dhwbi %0, 0" : : "a"(addr));
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addr += XCHAL_DCACHE_LINESIZE;
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}
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asm volatile(" dsync");
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}
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}
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#endif /* __KERNEL__ */
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#endif /* _XTENSA_CACHEFLUSH_H */
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