forked from luck/tmp_suning_uos_patched
84613387cb
Patch from Alessandro Zummo This patch fixes AHB/PCI endianness problems when the processor is in little-endian mode. The patch configures the CSR register closely following the directives in [1], paragraph 4.1, page 19. According to the considerations in [1], page 11, while the AHB bus supports both endian modes, on the IXP4XX it always uses big-endian. The PCI bus is connected to the South AHB. A wrong setting in the CSR register will thus cause a malfunctional PCI bus. A schematic diagram of the bus interconnections on the IXP4XX can be found in [1], page 18. The patch has been verified to work on the NSLU2 in both LE and BE modes. The author is Peter Korsgaard. [1] Intel® IXP4XX Product Line of Network Processors and IXC1100 Control Plane Processor: Understanding Big Endian and Little Endian Modes http://www.intel.com/design/network/applnots/25423701.pdf Signed-off-by: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
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| .. | ||
| common-pci.c | ||
| common.c | ||
| coyote-pci.c | ||
| coyote-setup.c | ||
| gtwx5715-pci.c | ||
| gtwx5715-setup.c | ||
| ixdp425-pci.c | ||
| ixdp425-setup.c | ||
| ixdpg425-pci.c | ||
| Kconfig | ||
| Makefile | ||
| Makefile.boot | ||