forked from luck/tmp_suning_uos_patched
3a0a401b40
Add dcr_base field to ocp_func_mal_data. This is preparation step for the new EMAC driver. Signed-off-by: Eugene Surovegin <ebs@ebshome.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
236 lines
6.9 KiB
C
236 lines
6.9 KiB
C
/*
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* arch/ppc/platforms/4xx/ibm440gx.c
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*
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* PPC440GX I/O descriptions
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*
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* Matt Porter <mporter@mvista.com>
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* Copyright 2002-2004 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <platforms/4xx/ibm440gx.h>
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#include <asm/ocp.h>
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#include <asm/ppc4xx_pic.h>
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static struct ocp_func_emac_data ibm440gx_emac0_def = {
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.rgmii_idx = -1, /* No RGMII */
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.rgmii_mux = -1, /* No RGMII */
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.zmii_idx = 0, /* ZMII device index */
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.zmii_mux = 0, /* ZMII input of this EMAC */
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.mal_idx = 0, /* MAL device index */
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.mal_rx_chan = 0, /* MAL rx channel number */
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.mal_tx_chan = 0, /* MAL tx channel number */
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.wol_irq = 61, /* WOL interrupt number */
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.mdio_idx = -1, /* No shared MDIO */
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.tah_idx = -1, /* No TAH */
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};
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static struct ocp_func_emac_data ibm440gx_emac1_def = {
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.rgmii_idx = -1, /* No RGMII */
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.rgmii_mux = -1, /* No RGMII */
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.zmii_idx = 0, /* ZMII device index */
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.zmii_mux = 1, /* ZMII input of this EMAC */
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.mal_idx = 0, /* MAL device index */
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.mal_rx_chan = 1, /* MAL rx channel number */
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.mal_tx_chan = 1, /* MAL tx channel number */
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.wol_irq = 63, /* WOL interrupt number */
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.mdio_idx = -1, /* No shared MDIO */
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.tah_idx = -1, /* No TAH */
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};
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static struct ocp_func_emac_data ibm440gx_emac2_def = {
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.rgmii_idx = 0, /* RGMII device index */
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.rgmii_mux = 0, /* RGMII input of this EMAC */
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.zmii_idx = 0, /* ZMII device index */
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.zmii_mux = 2, /* ZMII input of this EMAC */
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.mal_idx = 0, /* MAL device index */
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.mal_rx_chan = 2, /* MAL rx channel number */
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.mal_tx_chan = 2, /* MAL tx channel number */
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.wol_irq = 65, /* WOL interrupt number */
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.mdio_idx = -1, /* No shared MDIO */
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.tah_idx = 0, /* TAH device index */
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.jumbo = 1, /* Jumbo frames supported */
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};
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static struct ocp_func_emac_data ibm440gx_emac3_def = {
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.rgmii_idx = 0, /* RGMII device index */
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.rgmii_mux = 1, /* RGMII input of this EMAC */
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.zmii_idx = 0, /* ZMII device index */
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.zmii_mux = 3, /* ZMII input of this EMAC */
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.mal_idx = 0, /* MAL device index */
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.mal_rx_chan = 3, /* MAL rx channel number */
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.mal_tx_chan = 3, /* MAL tx channel number */
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.wol_irq = 67, /* WOL interrupt number */
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.mdio_idx = -1, /* No shared MDIO */
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.tah_idx = 1, /* TAH device index */
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.jumbo = 1, /* Jumbo frames supported */
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};
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OCP_SYSFS_EMAC_DATA()
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static struct ocp_func_mal_data ibm440gx_mal0_def = {
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.num_tx_chans = 4, /* Number of TX channels */
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.num_rx_chans = 4, /* Number of RX channels */
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.txeob_irq = 10, /* TX End Of Buffer IRQ */
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.rxeob_irq = 11, /* RX End Of Buffer IRQ */
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.txde_irq = 33, /* TX Descriptor Error IRQ */
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.rxde_irq = 34, /* RX Descriptor Error IRQ */
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.serr_irq = 32, /* MAL System Error IRQ */
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.dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
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};
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OCP_SYSFS_MAL_DATA()
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static struct ocp_func_iic_data ibm440gx_iic0_def = {
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.fast_mode = 0, /* Use standad mode (100Khz) */
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};
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static struct ocp_func_iic_data ibm440gx_iic1_def = {
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.fast_mode = 0, /* Use standad mode (100Khz) */
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};
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OCP_SYSFS_IIC_DATA()
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struct ocp_def core_ocp[] = {
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_OPB,
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.index = 0,
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.paddr = 0x0000000140000000ULL,
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.irq = OCP_IRQ_NA,
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.pm = OCP_CPM_NA,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_16550,
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.index = 0,
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.paddr = PPC440GX_UART0_ADDR,
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.irq = UART0_INT,
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.pm = IBM_CPM_UART0,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_16550,
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.index = 1,
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.paddr = PPC440GX_UART1_ADDR,
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.irq = UART1_INT,
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.pm = IBM_CPM_UART1,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_IIC,
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.index = 0,
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.paddr = 0x0000000140000400ULL,
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.irq = 2,
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.pm = IBM_CPM_IIC0,
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.additions = &ibm440gx_iic0_def,
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.show = &ocp_show_iic_data
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_IIC,
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.index = 1,
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.paddr = 0x0000000140000500ULL,
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.irq = 3,
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.pm = IBM_CPM_IIC1,
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.additions = &ibm440gx_iic1_def,
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.show = &ocp_show_iic_data
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_GPIO,
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.index = 0,
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.paddr = 0x0000000140000700ULL,
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.irq = OCP_IRQ_NA,
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.pm = IBM_CPM_GPIO0,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_MAL,
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.paddr = OCP_PADDR_NA,
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.irq = OCP_IRQ_NA,
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.pm = OCP_CPM_NA,
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.additions = &ibm440gx_mal0_def,
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.show = &ocp_show_mal_data,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_EMAC,
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.index = 0,
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.paddr = 0x0000000140000800ULL,
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.irq = 60,
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.pm = OCP_CPM_NA,
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.additions = &ibm440gx_emac0_def,
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.show = &ocp_show_emac_data,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_EMAC,
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.index = 1,
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.paddr = 0x0000000140000900ULL,
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.irq = 62,
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.pm = OCP_CPM_NA,
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.additions = &ibm440gx_emac1_def,
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.show = &ocp_show_emac_data,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_EMAC,
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.index = 2,
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.paddr = 0x0000000140000C00ULL,
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.irq = 64,
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.pm = OCP_CPM_NA,
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.additions = &ibm440gx_emac2_def,
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.show = &ocp_show_emac_data,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_EMAC,
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.index = 3,
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.paddr = 0x0000000140000E00ULL,
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.irq = 66,
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.pm = OCP_CPM_NA,
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.additions = &ibm440gx_emac3_def,
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.show = &ocp_show_emac_data,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_RGMII,
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.paddr = 0x0000000140000790ULL,
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.irq = OCP_IRQ_NA,
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.pm = OCP_CPM_NA,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_ZMII,
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.paddr = 0x0000000140000780ULL,
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.irq = OCP_IRQ_NA,
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.pm = OCP_CPM_NA,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_TAH,
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.index = 0,
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.paddr = 0x0000000140000b50ULL,
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.irq = 68,
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.pm = OCP_CPM_NA,
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},
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{ .vendor = OCP_VENDOR_IBM,
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.function = OCP_FUNC_TAH,
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.index = 1,
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.paddr = 0x0000000140000d50ULL,
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.irq = 69,
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.pm = OCP_CPM_NA,
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},
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{ .vendor = OCP_VENDOR_INVALID
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}
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};
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/* Polarity and triggering settings for internal interrupt sources */
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struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
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{ .polarity = 0xfffffe03,
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.triggering = 0x01c00000,
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.ext_irq_mask = 0x000001fc, /* IRQ0 - IRQ6 */
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},
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{ .polarity = 0xffffc0ff,
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.triggering = 0x00ff8000,
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.ext_irq_mask = 0x00003f00, /* IRQ7 - IRQ12 */
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},
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{ .polarity = 0xffff83ff,
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.triggering = 0x000f83c0,
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.ext_irq_mask = 0x00007c00, /* IRQ13 - IRQ17 */
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},
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};
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