forked from luck/tmp_suning_uos_patched
4cab5bf616
The driver now supports i.MX8MQ, so update bindings accordingly. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
65 lines
2.3 KiB
C
65 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Zodiac Inflight Innovations
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*/
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#ifndef DT_BINDING_RESET_IMX8MQ_H
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#define DT_BINDING_RESET_IMX8MQ_H
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#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0
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#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1
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#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2
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#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3
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#define IMX8MQ_RESET_A53_CORE_RESET0 4
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#define IMX8MQ_RESET_A53_CORE_RESET1 5
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#define IMX8MQ_RESET_A53_CORE_RESET2 6
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#define IMX8MQ_RESET_A53_CORE_RESET3 7
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#define IMX8MQ_RESET_A53_DBG_RESET0 8
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#define IMX8MQ_RESET_A53_DBG_RESET1 9
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#define IMX8MQ_RESET_A53_DBG_RESET2 10
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#define IMX8MQ_RESET_A53_DBG_RESET3 11
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#define IMX8MQ_RESET_A53_ETM_RESET0 12
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#define IMX8MQ_RESET_A53_ETM_RESET1 13
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#define IMX8MQ_RESET_A53_ETM_RESET2 14
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#define IMX8MQ_RESET_A53_ETM_RESET3 15
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#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16
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#define IMX8MQ_RESET_A53_L2RESET 17
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#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18
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#define IMX8MQ_RESET_OTG1_PHY_RESET 19
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#define IMX8MQ_RESET_OTG2_PHY_RESET 20
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#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21
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#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22
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#define IMX8MQ_RESET_MIPI_DIS_DPI_RESET_N 23
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#define IMX8MQ_RESET_MIPI_DIS_ESC_RESET_N 24
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#define IMX8MQ_RESET_MIPI_DIS_PCLK_RESET_N 25
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#define IMX8MQ_RESET_PCIEPHY 26
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#define IMX8MQ_RESET_PCIEPHY_PERST 27
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#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28
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#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29
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#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30
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#define IMX8MQ_RESET_DISP_RESET 31
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#define IMX8MQ_RESET_GPU_RESET 32
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#define IMX8MQ_RESET_VPU_RESET 33
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#define IMX8MQ_RESET_PCIEPHY2 34
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#define IMX8MQ_RESET_PCIEPHY2_PERST 35
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#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36
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#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37
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#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38
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#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39
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#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40
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#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41
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#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42
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#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43
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#define IMX8MQ_RESET_DDRC1_PRST 44
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#define IMX8MQ_RESET_DDRC1_CORE_RESET 45
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#define IMX8MQ_RESET_DDRC1_PHY_RESET 46
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#define IMX8MQ_RESET_DDRC2_PRST 47
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#define IMX8MQ_RESET_DDRC2_CORE_RESET 48
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#define IMX8MQ_RESET_DDRC2_PHY_RESET 49
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#define IMX8MQ_RESET_NUM 50
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#endif
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