forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/*
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* include/asm-v850/v850e2.h -- Machine-dependent defs for V850E2 CPUs
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*
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* Copyright (C) 2002,03 NEC Electronics Corporation
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* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_V850E2_H__
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#define __V850_V850E2_H__
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#include <asm/v850e_intc.h> /* v850e-style interrupt system. */
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#define CPU_ARCH "v850e2"
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/* Control registers. */
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/* Chip area select control */
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#define V850E2_CSC_ADDR(n) (0xFFFFF060 + (n) * 2)
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#define V850E2_CSC(n) (*(volatile u16 *)V850E2_CSC_ADDR(n))
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/* I/O area select control */
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#define V850E2_BPC_ADDR 0xFFFFF064
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#define V850E2_BPC (*(volatile u16 *)V850E2_BPC_ADDR)
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/* Bus size configuration */
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#define V850E2_BSC_ADDR 0xFFFFF066
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#define V850E2_BSC (*(volatile u16 *)V850E2_BSC_ADDR)
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/* Endian configuration */
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#define V850E2_BEC_ADDR 0xFFFFF068
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#define V850E2_BEC (*(volatile u16 *)V850E2_BEC_ADDR)
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/* Cache configuration */
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#define V850E2_BHC_ADDR 0xFFFFF06A
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#define V850E2_BHC (*(volatile u16 *)V850E2_BHC_ADDR)
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/* NPB strobe-wait configuration */
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#define V850E2_VSWC_ADDR 0xFFFFF06E
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#define V850E2_VSWC (*(volatile u16 *)V850E2_VSWC_ADDR)
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/* Bus cycle type */
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#define V850E2_BCT_ADDR(n) (0xFFFFF480 + (n) * 2)
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#define V850E2_BCT(n) (*(volatile u16 *)V850E2_BCT_ADDR(n))
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/* Data wait control */
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#define V850E2_DWC_ADDR(n) (0xFFFFF484 + (n) * 2)
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#define V850E2_DWC(n) (*(volatile u16 *)V850E2_DWC_ADDR(n))
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/* Bus cycle control */
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#define V850E2_BCC_ADDR 0xFFFFF488
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#define V850E2_BCC (*(volatile u16 *)V850E2_BCC_ADDR)
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/* Address wait control */
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#define V850E2_ASC_ADDR 0xFFFFF48A
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#define V850E2_ASC (*(volatile u16 *)V850E2_ASC_ADDR)
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/* Local bus sizing control */
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#define V850E2_LBS_ADDR 0xFFFFF48E
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#define V850E2_LBS (*(volatile u16 *)V850E2_LBS_ADDR)
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/* Line buffer control */
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#define V850E2_LBC_ADDR(n) (0xFFFFF490 + (n) * 2)
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#define V850E2_LBC(n) (*(volatile u16 *)V850E2_LBC_ADDR(n))
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/* SDRAM configuration */
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#define V850E2_SCR_ADDR(n) (0xFFFFF4A0 + (n) * 4)
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#define V850E2_SCR(n) (*(volatile u16 *)V850E2_SCR_ADDR(n))
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/* SDRAM refresh cycle control */
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#define V850E2_RFS_ADDR(n) (0xFFFFF4A2 + (n) * 4)
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#define V850E2_RFS(n) (*(volatile u16 *)V850E2_RFS_ADDR(n))
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#endif /* __V850_V850E2_H__ */
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