Matt Redfearn 21da533232 MIPS: Introduce cpu_tcache_line_size ... There exist macros to return the cache line size of the L1 dcache and L2 scache but there is currently no macro for the L3 tcache. Add this macro which will be used by the following patch "MIPS: PCI: Fix smp_processor_id() in preemptible" Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/16871/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2017-08-08 00:02:27 +02:00
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asm	MIPS: Introduce cpu_tcache_line_size	2017-08-08 00:02:27 +02:00
uapi/asm	tty: Fix TIOCGPTPEER ioctl definition	2017-07-17 17:04:41 +02:00