forked from luck/tmp_suning_uos_patched
1a4b0fc503
Fix MSPEC driver to build for non SN2 enabled configs as the driver should work in cached and uncached modes (no fetchop) on these systems. In addition make MSPEC select IA64_UNCACHED_ALLOCATOR, which is required for it and move it to arch/ia64/Kconfig to avoid warnings on non ia64 architectures running allmodconfig. Once the Kconfig code is fixed, we can move it back. Signed-off-by: Jes Sorensen <jes@sgi.com> Cc: Fernando Luis Vzquez Cao <fernando@oss.ntt.co.jp> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
300 lines
9.7 KiB
C
300 lines
9.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_IA64_SN_ADDRS_H
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#define _ASM_IA64_SN_ADDRS_H
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#include <asm/percpu.h>
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#include <asm/sn/types.h>
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#include <asm/sn/arch.h>
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#include <asm/sn/pda.h>
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/*
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* Memory/SHUB Address Format:
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* +-+---------+--+--------------+
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* |0| NASID |AS| NodeOffset |
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* +-+---------+--+--------------+
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*
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* NASID: (low NASID bit is 0) Memory and SHUB MMRs
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* AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
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* 00: Local Resources and MMR space
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* Top bit of NodeOffset
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* 0: Local resources space
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* node id:
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* 0: IA64/NT compatibility space
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* 2: Local MMR Space
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* 4: Local memory, regardless of local node id
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* 1: Global MMR space
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* 01: GET space.
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* 10: AMO space.
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* 11: Cacheable memory space.
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*
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* NodeOffset: byte offset
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*
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*
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* TIO address format:
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* +-+----------+--+--------------+
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* |0| NASID |AS| Nodeoffset |
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* +-+----------+--+--------------+
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*
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* NASID: (low NASID bit is 1) TIO
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* AS: 2-bit Chiplet Identifier
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* 00: TIO LB (Indicates TIO MMR access.)
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* 01: TIO ICE (indicates coretalk space access.)
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*
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* NodeOffset: top bit must be set.
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*
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*
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* Note that in both of the above address formats, the low
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* NASID bit indicates if the reference is to the SHUB or TIO MMRs.
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*/
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/*
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* Define basic shift & mask constants for manipulating NASIDs and AS values.
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*/
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#define NASID_BITMASK (sn_hub_info->nasid_bitmask)
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#define NASID_SHIFT (sn_hub_info->nasid_shift)
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#define AS_SHIFT (sn_hub_info->as_shift)
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#define AS_BITMASK 0x3UL
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#define NASID_MASK ((u64)NASID_BITMASK << NASID_SHIFT)
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#define AS_MASK ((u64)AS_BITMASK << AS_SHIFT)
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/*
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* AS values. These are the same on both SHUB1 & SHUB2.
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*/
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#define AS_GET_VAL 1UL
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#define AS_AMO_VAL 2UL
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#define AS_CAC_VAL 3UL
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#define AS_GET_SPACE (AS_GET_VAL << AS_SHIFT)
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#define AS_AMO_SPACE (AS_AMO_VAL << AS_SHIFT)
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#define AS_CAC_SPACE (AS_CAC_VAL << AS_SHIFT)
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/*
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* Virtual Mode Local & Global MMR space.
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*/
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#define SH1_LOCAL_MMR_OFFSET 0x8000000000UL
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#define SH2_LOCAL_MMR_OFFSET 0x0200000000UL
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#define LOCAL_MMR_OFFSET (is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
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#define LOCAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
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#define LOCAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
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#define SH1_GLOBAL_MMR_OFFSET 0x0800000000UL
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#define SH2_GLOBAL_MMR_OFFSET 0x0300000000UL
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#define GLOBAL_MMR_OFFSET (is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
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#define GLOBAL_MMR_SPACE (__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
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/*
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* Physical mode addresses
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*/
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#define GLOBAL_PHYS_MMR_SPACE (RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
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/*
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* Clear region & AS bits.
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*/
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#define TO_PHYS_MASK (~(RGN_BITS | AS_MASK))
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/*
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* Misc NASID manipulation.
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*/
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#define NASID_SPACE(n) ((u64)(n) << NASID_SHIFT)
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#define REMOTE_ADDR(n,a) (NASID_SPACE(n) | (a))
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#define NODE_OFFSET(x) ((x) & (NODE_ADDRSPACE_SIZE - 1))
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#define NODE_ADDRSPACE_SIZE (1UL << AS_SHIFT)
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#define NASID_GET(x) (int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
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#define LOCAL_MMR_ADDR(a) (LOCAL_MMR_SPACE | (a))
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#define GLOBAL_MMR_ADDR(n,a) (GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
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#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
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#define GLOBAL_CAC_ADDR(n,a) (CAC_BASE | REMOTE_ADDR(n,a))
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#define CHANGE_NASID(n,x) ((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
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#define IS_TIO_NASID(n) ((n) & 1)
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/* non-II mmr's start at top of big window space (4G) */
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#define BWIN_TOP 0x0000000100000000UL
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/*
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* general address defines
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*/
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#define CAC_BASE (PAGE_OFFSET | AS_CAC_SPACE)
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#define AMO_BASE (__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
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#define AMO_PHYS_BASE (RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
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#define GET_BASE (PAGE_OFFSET | AS_GET_SPACE)
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/*
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* Convert Memory addresses between various addressing modes.
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*/
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#define TO_PHYS(x) (TO_PHYS_MASK & (x))
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#define TO_CAC(x) (CAC_BASE | TO_PHYS(x))
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#ifdef CONFIG_SGI_SN
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#define TO_AMO(x) (AMO_BASE | TO_PHYS(x))
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#define TO_GET(x) (GET_BASE | TO_PHYS(x))
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#else
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#define TO_AMO(x) ({ BUG(); x; })
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#define TO_GET(x) ({ BUG(); x; })
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#endif
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/*
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* Covert from processor physical address to II/TIO physical address:
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* II - squeeze out the AS bits
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* TIO- requires a chiplet id in bits 38-39. For DMA to memory,
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* the chiplet id is zero. If we implement TIO-TIO dma, we might need
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* to insert a chiplet id into this macro. However, it is our belief
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* right now that this chiplet id will be ICE, which is also zero.
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*/
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#define SH1_TIO_PHYS_TO_DMA(x) \
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((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
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#define SH2_NETWORK_BANK_OFFSET(x) \
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((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
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#define SH2_NETWORK_BANK_SELECT(x) \
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((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4))) \
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>> (sn_hub_info->nasid_shift - 4)) << 36)
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#define SH2_NETWORK_ADDRESS(x) \
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(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
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#define SH2_TIO_PHYS_TO_DMA(x) \
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(((u64)(NASID_GET(x)) << 40) | SH2_NETWORK_ADDRESS(x))
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#define PHYS_TO_TIODMA(x) \
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(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
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#define PHYS_TO_DMA(x) \
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((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
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/*
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* Macros to test for address type.
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*/
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#define IS_AMO_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
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#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
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/*
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* The following definitions pertain to the IO special address
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* space. They define the location of the big and little windows
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* of any given node.
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*/
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#define BWIN_SIZE_BITS 29 /* big window size: 512M */
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#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
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#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
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: RAW_NODE_SWIN_BASE(n, w))
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#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
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((u64) (w) << TIO_SWIN_SIZE_BITS))
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#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
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#define TIO_IO_BASE(n) (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
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#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
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#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
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#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
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#define RAW_NODE_SWIN_BASE(n, w) (NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
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#define BWIN_WIDGET_MASK 0x7
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#define BWIN_WINDOWNUM(x) (((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
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#define SH1_IS_BIG_WINDOW_ADDR(x) ((x) & BWIN_TOP)
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#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
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#define TIO_BWIN_WINDOWNUM(x) (((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
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#define TIO_HWIN_SHIFT_BITS 33
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#define TIO_HWIN(x) (NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
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/*
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* The following definitions pertain to the IO special address
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* space. They define the location of the big and little windows
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* of any given node.
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*/
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#define SWIN_SIZE_BITS 24
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#define SWIN_WIDGET_MASK 0xF
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#define TIO_SWIN_SIZE_BITS 28
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#define TIO_SWIN_SIZE (1UL << TIO_SWIN_SIZE_BITS)
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#define TIO_SWIN_WIDGET_MASK 0x3
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/*
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* Convert smallwindow address to xtalk address.
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*
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* 'addr' can be physical or virtual address, but will be converted
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* to Xtalk address in the range 0 -> SWINZ_SIZEMASK
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*/
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#define SWIN_WIDGETNUM(x) (((x) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
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#define TIO_SWIN_WIDGETNUM(x) (((x) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
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/*
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* The following macros produce the correct base virtual address for
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* the hub registers. The REMOTE_HUB_* macro produce
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* the address for the specified hub's registers. The intent is
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* that the appropriate PI, MD, NI, or II register would be substituted
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* for x.
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*
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* WARNING:
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* When certain Hub chip workaround are defined, it's not sufficient
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* to dereference the *_HUB_ADDR() macros. You should instead use
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* HUB_L() and HUB_S() if you must deal with pointers to hub registers.
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* Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
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* They're always safe.
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*/
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/* Shub1 TIO & MMR addressing macros */
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#define SH1_TIO_IOSPACE_ADDR(n,x) \
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GLOBAL_MMR_ADDR(n,x)
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#define SH1_REMOTE_BWIN_MMR(n,x) \
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GLOBAL_MMR_ADDR(n,x)
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#define SH1_REMOTE_SWIN_MMR(n,x) \
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(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
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#define SH1_REMOTE_MMR(n,x) \
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(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) : \
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SH1_REMOTE_SWIN_MMR(n,x))
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/* Shub1 TIO & MMR addressing macros */
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#define SH2_TIO_IOSPACE_ADDR(n,x) \
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((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
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#define SH2_REMOTE_MMR(n,x) \
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GLOBAL_MMR_ADDR(n,x)
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/* TIO & MMR addressing macros that work on both shub1 & shub2 */
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#define TIO_IOSPACE_ADDR(n,x) \
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((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) : \
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SH2_TIO_IOSPACE_ADDR(n,x)))
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#define SH_REMOTE_MMR(n,x) \
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(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
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#define REMOTE_HUB_ADDR(n,x) \
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(IS_TIO_NASID(n) ? ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) : \
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((volatile u64*)SH_REMOTE_MMR(n,x)))
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#define HUB_L(x) (*((volatile typeof(*x) *)x))
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#define HUB_S(x,d) (*((volatile typeof(*x) *)x) = (d))
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#define REMOTE_HUB_L(n, a) HUB_L(REMOTE_HUB_ADDR((n), (a)))
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#define REMOTE_HUB_S(n, a, d) HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
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/*
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* Coretalk address breakdown
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*/
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#define CTALK_NASID_SHFT 40
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#define CTALK_NASID_MASK (0x3FFFULL << CTALK_NASID_SHFT)
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#define CTALK_CID_SHFT 38
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#define CTALK_CID_MASK (0x3ULL << CTALK_CID_SHFT)
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#define CTALK_NODE_OFFSET 0x3FFFFFFFFF
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#endif /* _ASM_IA64_SN_ADDRS_H */
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