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Zhou Wang dfed0098ab crypto: hisilicon - add hardware SGL support
HiSilicon accelerators in Hip08 use same hardware scatterlist for data format.
We support it in this module.

Specific accelerator drivers can use hisi_acc_create_sgl_pool to allocate
hardware SGLs ahead. Then use hisi_acc_sg_buf_map_to_hw_sgl to get one
hardware SGL and pass related information to hardware SGL.

The DMA address of mapped hardware SGL can be passed to SGL src/dst field
in QM SQE.

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2019-08-09 15:11:53 +10:00
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crypto crypto: engine - Reduce default RT priority 2019-08-09 15:11:52 +10:00
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include crypto: aes - helper function to validate key length for AES algorithms 2019-08-09 15:11:43 +10:00
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lib crypto: aes - helper function to validate key length for AES algorithms 2019-08-09 15:11:43 +10:00
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