forked from luck/tmp_suning_uos_patched
a5f6ea29f9
Commit bcf24e1daa ("mmc: omap_hsmmc: use the generic config for
omap2plus devices"), enabled the build for other platforms for compile
testing.
sh-allmodconfig now fails with:
include/linux/omap-dma.h:171:8: error: expected identifier before numeric constant
make[4]: *** [drivers/mmc/host/omap_hsmmc.o] Error 1
This happens because SuperH #defines "CCR", which is one of the enum
values in include/linux/omap-dma.h. There's a similar issue with "CCR2"
on sh2a.
As "CCR" and "CCR2" are too generic names for global #defines, prefix
them with "SH_" to fix this.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/*
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* include/asm-sh/cpu-sh3/cache.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH3_CACHE_H
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#define __ASM_CPU_SH3_CACHE_H
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#define L1_CACHE_SHIFT 4
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#define SH_CACHE_VALID 1
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#define SH_CACHE_UPDATED 2
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#define SH_CACHE_COMBINED 4
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#define SH_CACHE_ASSOC 8
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#define SH_CCR 0xffffffec /* Address of Cache Control Register */
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#define CCR_CACHE_CE 0x01 /* Cache Enable */
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#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
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#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
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#define CCR_CACHE_CF 0x08 /* Cache Flush */
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#define CCR_CACHE_ORA 0x20 /* RAM mode */
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#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_PHYSADDR_MASK 0x1ffffc00
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#define CCR_CACHE_ENABLE CCR_CACHE_CE
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#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
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#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710) || \
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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#define CCR3_REG 0xa40000b4
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#define CCR_CACHE_16KB 0x00010000
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#define CCR_CACHE_32KB 0x00020000
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#endif
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#endif /* __ASM_CPU_SH3_CACHE_H */
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