AcoSail/kernel_optimize_test
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kernel_optimize_test/include/dt-bindings/memory
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Thierry Reding 029ab5eaf0 dt-bindings: memory: Add Tegra186 support 
As opposed to earlier incarnations, the memory controller on Tegra186 no
longer implements an SMMU. Instead the SMMU is a regular ARM SMMU and in
a separate IP block.

However, the memory controller programs the SMMU stream IDs for each of
the memory clients. Add a header file with definitions for each of these
stream IDs and mark the #iommu-cells property as required on Tegra30 to
Tegra210 in the device tree bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-12-13 12:53:43 +01:00
..
mt2701-larb-port.h iommu/mediatek: dt-binding: Correct the larb port offset defines for mt2701 2016-08-22 12:52:10 +02:00
mt8173-larb-port.h iommu/mediatek: Move MTK_M4U_TO_LARB/PORT into mtk_iommu.c 2017-08-22 16:37:58 +02:00
tegra30-mc.h License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
tegra114-mc.h License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
tegra124-mc.h License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
tegra186-mc.h dt-bindings: memory: Add Tegra186 support 2017-12-13 12:53:43 +01:00
tegra210-mc.h License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00