forked from luck/tmp_suning_uos_patched
abda1bd5f4
Convert some of the sleep.S guts to C code, which makes it easier to use our macros and to add L2 cache handling. We provide a helper function, __cpu_suspend_save(), which deals with saving the common state, setting up for resume, and flushing caches. The remainder left as assembly code is the saving of the CPU general purpose registers, and allocating space on the stack to save the CPU specific registers and resume state. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
102 lines
2.7 KiB
ArmAsm
102 lines
2.7 KiB
ArmAsm
#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/glue-cache.h>
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#include <asm/glue-proc.h>
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#include <asm/system.h>
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.text
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/*
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* Save CPU state for a suspend. This saves the CPU general purpose
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* registers, and allocates space on the kernel stack to save the CPU
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* specific registers and some other data for resume.
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* r0 = suspend function arg0
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* r1 = suspend function
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*/
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ENTRY(__cpu_suspend)
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stmfd sp!, {r4 - r11, lr}
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#ifdef MULTI_CPU
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ldr r10, =processor
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ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
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#else
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ldr r4, =cpu_suspend_size
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#endif
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mov r5, sp @ current virtual SP
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add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn
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sub sp, sp, r4 @ allocate CPU state on stack
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stmfd sp!, {r0, r1} @ save suspend func arg and pointer
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add r0, sp, #8 @ save pointer to save block
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mov r1, r4 @ size of save block
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mov r2, r5 @ virtual SP
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ldr r3, =sleep_save_sp
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
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ALT_UP(mov lr, #0)
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and lr, lr, #15
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add r3, r3, lr, lsl #2
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#endif
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bl __cpu_suspend_save
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adr lr, BSYM(cpu_suspend_abort)
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ldmfd sp!, {r0, pc} @ call suspend fn
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ENDPROC(__cpu_suspend)
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.ltorg
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cpu_suspend_abort:
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ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
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teq r0, #0
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moveq r0, #1 @ force non-zero value
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mov sp, r2
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_suspend_abort)
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/*
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* r0 = control register value
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*/
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.align 5
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ENTRY(cpu_resume_mmu)
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ldr r3, =cpu_resume_after_mmu
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mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r0, c0, c0, 0 @ read id reg
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mov r0, r0
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mov r0, r0
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mov pc, r3 @ jump to virtual address
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ENDPROC(cpu_resume_mmu)
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cpu_resume_after_mmu:
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bl cpu_init @ restore the und/abt/irq banked regs
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mov r0, #0 @ return zero on success
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(cpu_resume_after_mmu)
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/*
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* Note: Yes, part of the following code is located into the .data section.
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* This is to allow sleep_save_sp to be accessed with a relative load
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* while we can't rely on any MMU translation. We could have put
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* sleep_save_sp in the .text section as well, but some setups might
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* insist on it to be truly read-only.
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*/
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.data
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.align
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ENTRY(cpu_resume)
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#ifdef CONFIG_SMP
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adr r0, sleep_save_sp
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ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
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ALT_UP(mov r1, #0)
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and r1, r1, #15
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ldr r0, [r0, r1, lsl #2] @ stack phys addr
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#else
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ldr r0, sleep_save_sp @ stack phys addr
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#endif
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
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@ load phys pgd, stack, resume fn
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ARM( ldmia r0!, {r1, sp, pc} )
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THUMB( ldmia r0!, {r1, r2, r3} )
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THUMB( mov sp, r2 )
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THUMB( bx r3 )
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ENDPROC(cpu_resume)
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sleep_save_sp:
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.rept CONFIG_NR_CPUS
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.long 0 @ preserve stack phys ptr here
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.endr
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