forked from luck/tmp_suning_uos_patched
97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
21 lines
561 B
C
21 lines
561 B
C
/*
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* include/asm-mips/irq_cpu.h
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*
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* MIPS CPU interrupt definitions.
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*
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* Copyright (C) 2002 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_IRQ_CPU_H
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#define _ASM_IRQ_CPU_H
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extern void mips_cpu_irq_init(void);
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extern void rm7k_cpu_irq_init(void);
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extern void rm9k_cpu_irq_init(void);
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#endif /* _ASM_IRQ_CPU_H */
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