kernel_optimize_test/arch/parisc
Helge Deller e6eb5fe912 parisc: Drop LDCW barrier in CAS code when running UP
When running an SMP kernel on a single-CPU machine, we can speed up the
CAS code by replacing the LDCW sync barrier with NOP.

Signed-off-by: Helge Deller <deller@gmx.de>
2019-05-10 21:00:24 +02:00
..
boot parisc: Use PA_ASM_LEVEL in boot code 2019-05-06 00:10:00 +02:00
configs
include parisc: Add static branch and JUMP_LABEL feature 2019-05-06 00:10:03 +02:00
kernel parisc: Drop LDCW barrier in CAS code when running UP 2019-05-10 21:00:24 +02:00
lib parisc: iomap: introduce io{read|write}64 2019-01-22 13:39:59 +01:00
math-emu
mm parisc: Update huge TLB page support to use per-pagetable spinlock 2019-05-03 23:47:41 +02:00
oprofile
defpalo.conf
install.sh
Kconfig parisc: Add static branch and JUMP_LABEL feature 2019-05-06 00:10:03 +02:00
Kconfig.debug
Makefile parisc: generate uapi header and system call table files 2018-12-10 08:26:04 +01:00
nm