Thierry Reding a213f9f1c3 dt-bindings: memory: Add Tegra194 memory controller header ... This header contains definitions for the memory controller found on NVIDIA Tegra194 SoCs, such as the stream IDs used for the ARM SMMU and the IDs used to identify the various memory clients. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Rob Herring <robh@kernel.org>		2020-01-09 19:10:27 +01:00
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mt2701-larb-port.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
mt2712-larb-port.h	dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI	2018-07-18 17:01:04 +02:00
mt8173-larb-port.h	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174	2019-05-30 11:26:41 -07:00
mt8183-larb-port.h	dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI	2019-08-30 15:57:26 +02:00
tegra20-mc.h
tegra30-mc.h
tegra114-mc.h
tegra124-mc.h
tegra186-mc.h	dt-bindings: memory: Add Tegra186 memory client IDs	2020-01-09 19:10:04 +01:00
tegra194-mc.h	dt-bindings: memory: Add Tegra194 memory controller header	2020-01-09 19:10:27 +01:00
tegra210-mc.h