forked from luck/tmp_suning_uos_patched
e98bed7f0f
Currently, when suspend is occurred, register im0/1 and gpio_use_sel are not saved. This patch modifies so that register im0/1 and gpio_use_sel are saved. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
366 lines
9.0 KiB
C
366 lines
9.0 KiB
C
/*
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* Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/gpio.h>
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struct pch_regs {
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u32 ien;
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u32 istatus;
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u32 idisp;
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u32 iclr;
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u32 imask;
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u32 imaskclr;
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u32 po;
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u32 pi;
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u32 pm;
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u32 im0;
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u32 im1;
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u32 reserved[3];
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u32 gpio_use_sel;
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u32 reset;
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};
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enum pch_type_t {
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INTEL_EG20T_PCH,
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OKISEMI_ML7223m_IOH, /* OKISEMI ML7223 IOH PCIe Bus-m */
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OKISEMI_ML7223n_IOH /* OKISEMI ML7223 IOH PCIe Bus-n */
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};
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/* Specifies number of GPIO PINS */
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static int gpio_pins[] = {
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[INTEL_EG20T_PCH] = 12,
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[OKISEMI_ML7223m_IOH] = 8,
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[OKISEMI_ML7223n_IOH] = 8,
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};
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/**
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* struct pch_gpio_reg_data - The register store data.
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* @po_reg: To store contents of PO register.
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* @pm_reg: To store contents of PM register.
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* @im0_reg: To store contents of IM0 register.
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* @im1_reg: To store contents of IM1 register.
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* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
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* (Only ML7223 Bus-n)
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*/
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struct pch_gpio_reg_data {
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u32 po_reg;
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u32 pm_reg;
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u32 im0_reg;
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u32 im1_reg;
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u32 gpio_use_sel_reg;
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};
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/**
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* struct pch_gpio - GPIO private data structure.
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* @base: PCI base address of Memory mapped I/O register.
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* @reg: Memory mapped PCH GPIO register list.
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* @dev: Pointer to device structure.
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* @gpio: Data for GPIO infrastructure.
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* @pch_gpio_reg: Memory mapped Register data is saved here
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* when suspend.
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* @ioh: IOH ID
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* @spinlock: Used for register access protection in
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* interrupt context pch_irq_mask,
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* pch_irq_unmask and pch_irq_type;
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*/
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struct pch_gpio {
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void __iomem *base;
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struct pch_regs __iomem *reg;
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struct device *dev;
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struct gpio_chip gpio;
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struct pch_gpio_reg_data pch_gpio_reg;
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struct mutex lock;
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enum pch_type_t ioh;
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spinlock_t spinlock;
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};
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static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
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{
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u32 reg_val;
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struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
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mutex_lock(&chip->lock);
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reg_val = ioread32(&chip->reg->po);
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if (val)
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reg_val |= (1 << nr);
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else
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reg_val &= ~(1 << nr);
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iowrite32(reg_val, &chip->reg->po);
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mutex_unlock(&chip->lock);
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}
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static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
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{
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struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
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return ioread32(&chip->reg->pi) & (1 << nr);
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}
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static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
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int val)
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{
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struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
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u32 pm;
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u32 reg_val;
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mutex_lock(&chip->lock);
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm |= (1 << nr);
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iowrite32(pm, &chip->reg->pm);
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reg_val = ioread32(&chip->reg->po);
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if (val)
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reg_val |= (1 << nr);
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else
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reg_val &= ~(1 << nr);
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iowrite32(reg_val, &chip->reg->po);
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mutex_unlock(&chip->lock);
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return 0;
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}
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static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
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{
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struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
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u32 pm;
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mutex_lock(&chip->lock);
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pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
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pm &= ~(1 << nr);
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iowrite32(pm, &chip->reg->pm);
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mutex_unlock(&chip->lock);
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return 0;
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}
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/*
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* Save register configuration and disable interrupts.
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*/
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static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
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{
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chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
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chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
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chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
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if (chip->ioh == INTEL_EG20T_PCH)
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chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
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if (chip->ioh == OKISEMI_ML7223n_IOH)
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chip->pch_gpio_reg.gpio_use_sel_reg =\
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ioread32(&chip->reg->gpio_use_sel);
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}
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/*
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* This function restores the register configuration of the GPIO device.
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*/
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static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
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{
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/* to store contents of PO register */
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iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
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/* to store contents of PM register */
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iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
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iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
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if (chip->ioh == INTEL_EG20T_PCH)
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iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
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if (chip->ioh == OKISEMI_ML7223n_IOH)
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iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
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&chip->reg->gpio_use_sel);
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}
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static void pch_gpio_setup(struct pch_gpio *chip)
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{
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struct gpio_chip *gpio = &chip->gpio;
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gpio->label = dev_name(chip->dev);
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gpio->owner = THIS_MODULE;
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gpio->direction_input = pch_gpio_direction_input;
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gpio->get = pch_gpio_get;
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gpio->direction_output = pch_gpio_direction_output;
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gpio->set = pch_gpio_set;
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gpio->dbg_show = NULL;
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gpio->base = -1;
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gpio->ngpio = gpio_pins[chip->ioh];
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gpio->can_sleep = 0;
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}
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static int __devinit pch_gpio_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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s32 ret;
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struct pch_gpio *chip;
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (chip == NULL)
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return -ENOMEM;
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chip->dev = &pdev->dev;
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
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goto err_pci_enable;
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}
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ret = pci_request_regions(pdev, KBUILD_MODNAME);
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if (ret) {
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dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
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goto err_request_regions;
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}
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chip->base = pci_iomap(pdev, 1, 0);
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if (chip->base == 0) {
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dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
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ret = -ENOMEM;
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goto err_iomap;
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}
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if (pdev->device == 0x8803)
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chip->ioh = INTEL_EG20T_PCH;
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else if (pdev->device == 0x8014)
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chip->ioh = OKISEMI_ML7223m_IOH;
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else if (pdev->device == 0x8043)
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chip->ioh = OKISEMI_ML7223n_IOH;
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chip->reg = chip->base;
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pci_set_drvdata(pdev, chip);
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mutex_init(&chip->lock);
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pch_gpio_setup(chip);
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ret = gpiochip_add(&chip->gpio);
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if (ret) {
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dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
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goto err_gpiochip_add;
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}
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return 0;
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err_gpiochip_add:
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pci_iounmap(pdev, chip->base);
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err_iomap:
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pci_release_regions(pdev);
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err_request_regions:
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pci_disable_device(pdev);
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err_pci_enable:
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kfree(chip);
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dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
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return ret;
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}
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static void __devexit pch_gpio_remove(struct pci_dev *pdev)
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{
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int err;
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struct pch_gpio *chip = pci_get_drvdata(pdev);
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err = gpiochip_remove(&chip->gpio);
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if (err)
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dev_err(&pdev->dev, "Failed gpiochip_remove\n");
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pci_iounmap(pdev, chip->base);
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pci_release_regions(pdev);
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pci_disable_device(pdev);
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kfree(chip);
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}
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#ifdef CONFIG_PM
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static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
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{
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s32 ret;
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struct pch_gpio *chip = pci_get_drvdata(pdev);
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unsigned long flags;
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spin_lock_irqsave(&chip->spinlock, flags);
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pch_gpio_save_reg_conf(chip);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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ret = pci_save_state(pdev);
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if (ret) {
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dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
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return ret;
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}
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pci_disable_device(pdev);
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pci_set_power_state(pdev, PCI_D0);
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ret = pci_enable_wake(pdev, PCI_D0, 1);
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if (ret)
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dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
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return 0;
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}
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static int pch_gpio_resume(struct pci_dev *pdev)
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{
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s32 ret;
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struct pch_gpio *chip = pci_get_drvdata(pdev);
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unsigned long flags;
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ret = pci_enable_wake(pdev, PCI_D0, 0);
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pci_set_power_state(pdev, PCI_D0);
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ret = pci_enable_device(pdev);
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if (ret) {
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dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
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return ret;
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}
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pci_restore_state(pdev);
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spin_lock_irqsave(&chip->spinlock, flags);
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iowrite32(0x01, &chip->reg->reset);
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iowrite32(0x00, &chip->reg->reset);
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pch_gpio_restore_reg_conf(chip);
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spin_unlock_irqrestore(&chip->spinlock, flags);
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return 0;
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}
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#else
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#define pch_gpio_suspend NULL
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#define pch_gpio_resume NULL
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#endif
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#define PCI_VENDOR_ID_ROHM 0x10DB
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static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
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{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
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{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
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static struct pci_driver pch_gpio_driver = {
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.name = "pch_gpio",
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.id_table = pch_gpio_pcidev_id,
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.probe = pch_gpio_probe,
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.remove = __devexit_p(pch_gpio_remove),
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.suspend = pch_gpio_suspend,
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.resume = pch_gpio_resume
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};
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static int __init pch_gpio_pci_init(void)
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{
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return pci_register_driver(&pch_gpio_driver);
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}
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module_init(pch_gpio_pci_init);
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static void __exit pch_gpio_pci_exit(void)
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{
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pci_unregister_driver(&pch_gpio_driver);
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}
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module_exit(pch_gpio_pci_exit);
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MODULE_DESCRIPTION("PCH GPIO PCI Driver");
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MODULE_LICENSE("GPL");
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