forked from luck/tmp_suning_uos_patched
24f287e412
When the cpu count is high and contention hits an atomic object, the processors can synchronize such that some cpus continually get knocked out and cannot complete the atomic update. So implement an exponential backoff when SMP. Signed-off-by: David S. Miller <davem@davemloft.net>
166 lines
3.1 KiB
ArmAsm
166 lines
3.1 KiB
ArmAsm
/* bitops.S: Sparc64 atomic bit operations.
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*
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* Copyright (C) 2000, 2007 David S. Miller (davem@davemloft.net)
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*/
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#include <asm/asi.h>
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#include <asm/backoff.h>
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.text
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/* On SMP we need to use memory barriers to ensure
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* correct memory operation ordering, nop these out
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* for uniprocessor.
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*/
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#ifdef CONFIG_SMP
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#define BITOP_PRE_BARRIER membar #StoreLoad | #LoadLoad
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#define BITOP_POST_BARRIER \
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ba,pt %xcc, 80b; \
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membar #StoreLoad | #StoreStore
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80: retl
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nop
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#else
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#define BITOP_PRE_BARRIER
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#define BITOP_POST_BARRIER
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#endif
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.globl test_and_set_bit
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.type test_and_set_bit,#function
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test_and_set_bit: /* %o0=nr, %o1=addr */
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BACKOFF_SETUP(%o3)
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BITOP_PRE_BARRIER
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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or %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 2f
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and %g7, %o2, %g2
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clr %o0
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movrne %g2, 1, %o0
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BITOP_POST_BARRIER
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retl
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nop
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2: BACKOFF_SPIN(%o3, %o4, 1b)
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.size test_and_set_bit, .-test_and_set_bit
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.globl test_and_clear_bit
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.type test_and_clear_bit,#function
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test_and_clear_bit: /* %o0=nr, %o1=addr */
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BACKOFF_SETUP(%o3)
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BITOP_PRE_BARRIER
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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andn %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 2f
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and %g7, %o2, %g2
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clr %o0
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movrne %g2, 1, %o0
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BITOP_POST_BARRIER
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retl
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nop
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2: BACKOFF_SPIN(%o3, %o4, 1b)
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.size test_and_clear_bit, .-test_and_clear_bit
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.globl test_and_change_bit
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.type test_and_change_bit,#function
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test_and_change_bit: /* %o0=nr, %o1=addr */
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BACKOFF_SETUP(%o3)
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BITOP_PRE_BARRIER
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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xor %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 2f
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and %g7, %o2, %g2
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clr %o0
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movrne %g2, 1, %o0
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BITOP_POST_BARRIER
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retl
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nop
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2: BACKOFF_SPIN(%o3, %o4, 1b)
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.size test_and_change_bit, .-test_and_change_bit
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.globl set_bit
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.type set_bit,#function
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set_bit: /* %o0=nr, %o1=addr */
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BACKOFF_SETUP(%o3)
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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or %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 2f
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nop
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retl
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nop
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2: BACKOFF_SPIN(%o3, %o4, 1b)
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.size set_bit, .-set_bit
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.globl clear_bit
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.type clear_bit,#function
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clear_bit: /* %o0=nr, %o1=addr */
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BACKOFF_SETUP(%o3)
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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andn %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 2f
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nop
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retl
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nop
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2: BACKOFF_SPIN(%o3, %o4, 1b)
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.size clear_bit, .-clear_bit
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.globl change_bit
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.type change_bit,#function
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change_bit: /* %o0=nr, %o1=addr */
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BACKOFF_SETUP(%o3)
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srlx %o0, 6, %g1
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mov 1, %o2
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sllx %g1, 3, %g3
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and %o0, 63, %g2
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sllx %o2, %g2, %o2
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add %o1, %g3, %o1
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1: ldx [%o1], %g7
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xor %g7, %o2, %g1
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casx [%o1], %g7, %g1
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cmp %g7, %g1
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bne,pn %xcc, 2f
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nop
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retl
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nop
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2: BACKOFF_SPIN(%o3, %o4, 1b)
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.size change_bit, .-change_bit
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