forked from luck/tmp_suning_uos_patched
96983ffefc
This extends commit a8ca8b64e3 to cover
MIPSxx-style board cache code.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
117 lines
2.5 KiB
C
117 lines
2.5 KiB
C
/*
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* Copyright (C) 2006 Chris Dearman (chris@mips.com),
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/mipsregs.h>
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#include <asm/bcache.h>
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#include <asm/cacheops.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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#include <asm/r4kcache.h>
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/*
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* MIPS32/MIPS64 L2 cache handling
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*/
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/*
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* Writeback and invalidate the secondary cache before DMA.
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*/
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static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
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{
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blast_scache_range(addr, addr + size);
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}
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/*
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* Invalidate the secondary cache before DMA.
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*/
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static void mips_sc_inv(unsigned long addr, unsigned long size)
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{
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unsigned long lsize = cpu_scache_line_size();
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unsigned long almask = ~(lsize - 1);
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cache_op(Hit_Writeback_Inv_SD, addr & almask);
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cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
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blast_inv_scache_range(addr, addr + size);
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}
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static void mips_sc_enable(void)
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{
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/* L2 cache is permanently enabled */
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}
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static void mips_sc_disable(void)
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{
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/* L2 cache is permanently enabled */
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}
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static struct bcache_ops mips_sc_ops = {
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.bc_enable = mips_sc_enable,
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.bc_disable = mips_sc_disable,
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.bc_wback_inv = mips_sc_wback_inv,
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.bc_inv = mips_sc_inv
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};
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static inline int __init mips_sc_probe(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int config1, config2;
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unsigned int tmp;
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/* Mark as not present until probe completed */
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c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
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/* Ignore anything but MIPSxx processors */
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if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
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c->isa_level != MIPS_CPU_ISA_M32R2 &&
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c->isa_level != MIPS_CPU_ISA_M64R1 &&
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c->isa_level != MIPS_CPU_ISA_M64R2)
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return 0;
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/* Does this MIPS32/MIPS64 CPU have a config2 register? */
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config1 = read_c0_config1();
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if (!(config1 & MIPS_CONF_M))
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return 0;
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config2 = read_c0_config2();
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tmp = (config2 >> 4) & 0x0f;
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if (0 < tmp && tmp <= 7)
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c->scache.linesz = 2 << tmp;
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else
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return 0;
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tmp = (config2 >> 8) & 0x0f;
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if (0 <= tmp && tmp <= 7)
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c->scache.sets = 64 << tmp;
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else
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return 0;
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tmp = (config2 >> 0) & 0x0f;
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if (0 <= tmp && tmp <= 7)
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c->scache.ways = tmp + 1;
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else
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return 0;
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c->scache.waysize = c->scache.sets * c->scache.linesz;
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c->scache.waybit = __ffs(c->scache.waysize);
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
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return 1;
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}
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int __cpuinit mips_sc_init(void)
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{
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int found = mips_sc_probe();
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if (found) {
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mips_sc_enable();
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bcops = &mips_sc_ops;
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}
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return found;
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}
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