forked from luck/tmp_suning_uos_patched
fb615d61b5
MIPS will soon not be a part of Imagination Technologies, and as such many @imgtec.com email addresses will no longer be valid. This patch updates the addresses for those who: - Have 10 or more patches in mainline authored using an @imgtec.com email address, or any patches dated within the past year. - Are still with Imagination but leaving as part of the MIPS business unit, as determined from an internal email address list. - Haven't already updated their email address (ie. JamesH) or expressed a desire to be excluded (ie. Maciej). - Acked v2 or earlier of this patch, which leaves Deng-Cheng, Matt & myself. New addresses are of the form firstname.lastname@mips.com, and all verified against an internal email address list. An entry is added to .mailmap for each person such that get_maintainer.pl will report the new addresses rather than @imgtec.com addresses which will soon be dead. Instances of the affected addresses throughout the tree are then mechanically replaced with the new @mips.com address. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@mips.com> Acked-by: Dengcheng Zhu <dengcheng.zhu@mips.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Matt Redfearn <matt.redfearn@mips.com> Acked-by: Matt Redfearn <matt.redfearn@mips.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
/*
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* Copyright (C) 2014 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_PM_CPS_H__
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#define __MIPS_ASM_PM_CPS_H__
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/*
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* The CM & CPC can only handle coherence & power control on a per-core basis,
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* thus in an MT system the VP(E)s within each core are coupled and can only
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* enter or exit states requiring CM or CPC assistance in unison.
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*/
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#if defined(CONFIG_CPU_MIPSR6)
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# define coupled_coherence cpu_has_vp
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#elif defined(CONFIG_MIPS_MT)
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# define coupled_coherence cpu_has_mipsmt
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#else
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# define coupled_coherence 0
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#endif
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/* Enumeration of possible PM states */
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enum cps_pm_state {
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CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
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CPS_PM_CLOCK_GATED, /* Core clock gated */
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CPS_PM_POWER_GATED, /* Core power gated */
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CPS_PM_STATE_COUNT,
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};
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/**
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* cps_pm_support_state - determine whether the system supports a PM state
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* @state: the state to test for support
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*
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* Returns true if the system supports the given state, otherwise false.
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*/
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extern bool cps_pm_support_state(enum cps_pm_state state);
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/**
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* cps_pm_enter_state - enter a PM state
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* @state: the state to enter
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*
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* Enter the given PM state. If coupled_coherence is non-zero then it is
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* expected that this function be called at approximately the same time on
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* each coupled CPU. Returns 0 on successful entry & exit, otherwise -errno.
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*/
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extern int cps_pm_enter_state(enum cps_pm_state state);
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#endif /* __MIPS_ASM_PM_CPS_H__ */
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