forked from luck/tmp_suning_uos_patched
d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* S3C2410 Internal RTC register definition
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*/
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#ifndef __ASM_ARCH_REGS_RTC_H
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#define __ASM_ARCH_REGS_RTC_H __FILE__
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#define S3C2410_RTCREG(x) (x)
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#define S3C2410_INTP S3C2410_RTCREG(0x30)
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#define S3C2410_INTP_ALM (1 << 1)
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#define S3C2410_INTP_TIC (1 << 0)
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#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
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#define S3C2410_RTCCON_RTCEN (1 << 0)
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#define S3C2410_RTCCON_CNTSEL (1 << 2)
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#define S3C2410_RTCCON_CLKRST (1 << 3)
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#define S3C2443_RTCCON_TICSEL (1 << 4)
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#define S3C64XX_RTCCON_TICEN (1 << 8)
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#define S3C2410_TICNT S3C2410_RTCREG(0x44)
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#define S3C2410_TICNT_ENABLE (1 << 7)
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/* S3C2443: tick count is 15 bit wide
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* TICNT[6:0] contains upper 7 bits
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* TICNT1[7:0] contains lower 8 bits
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*/
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#define S3C2443_TICNT_PART(x) ((x & 0x7f00) >> 8)
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#define S3C2443_TICNT1 S3C2410_RTCREG(0x4C)
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#define S3C2443_TICNT1_PART(x) (x & 0xff)
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/* S3C2416: tick count is 32 bit wide
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* TICNT[6:0] contains bits [14:8]
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* TICNT1[7:0] contains lower 8 bits
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* TICNT2[16:0] contains upper 17 bits
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*/
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#define S3C2416_TICNT2 S3C2410_RTCREG(0x48)
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#define S3C2416_TICNT2_PART(x) ((x & 0xffff8000) >> 15)
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#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
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#define S3C2410_RTCALM_ALMEN (1 << 6)
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#define S3C2410_RTCALM_YEAREN (1 << 5)
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#define S3C2410_RTCALM_MONEN (1 << 4)
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#define S3C2410_RTCALM_DAYEN (1 << 3)
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#define S3C2410_RTCALM_HOUREN (1 << 2)
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#define S3C2410_RTCALM_MINEN (1 << 1)
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#define S3C2410_RTCALM_SECEN (1 << 0)
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#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
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#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
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#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
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#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
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#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
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#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
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#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
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#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
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#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
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#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
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#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
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#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
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#endif /* __ASM_ARCH_REGS_RTC_H */
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