forked from luck/tmp_suning_uos_patched
24ef7fc4dc
We need some more page flags to hook up _PAGE_WIRED (and eventually other things). So use the unused PTE bits above the PPN field as no implementations use these for anything currently. Now that we have _PAGE_WIRED let's provide the SH-5 functions for wiring up TLB entries. Signed-off-by: Matt Fleming <matt@console-pimps.org>
169 lines
3.7 KiB
C
169 lines
3.7 KiB
C
#ifndef __ASM_SH_TLB_H
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#define __ASM_SH_TLB_H
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#ifdef CONFIG_SUPERH64
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# include "tlb_64.h"
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#endif
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#ifndef __ASSEMBLY__
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#include <linux/pagemap.h>
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#ifdef CONFIG_MMU
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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/*
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* TLB handling. This allows us to remove pages from the page
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* tables, and efficiently handle the TLB issues.
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*/
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struct mmu_gather {
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struct mm_struct *mm;
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unsigned int fullmm;
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unsigned long start, end;
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};
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DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
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static inline void init_tlb_gather(struct mmu_gather *tlb)
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{
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tlb->start = TASK_SIZE;
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tlb->end = 0;
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if (tlb->fullmm) {
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tlb->start = 0;
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tlb->end = TASK_SIZE;
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}
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}
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static inline struct mmu_gather *
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tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
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{
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struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
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tlb->mm = mm;
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tlb->fullmm = full_mm_flush;
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init_tlb_gather(tlb);
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return tlb;
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}
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static inline void
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tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
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{
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if (tlb->fullmm)
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flush_tlb_mm(tlb->mm);
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/* keep the page table cache within bounds */
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check_pgt_cache();
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put_cpu_var(mmu_gathers);
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}
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static inline void
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tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
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{
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if (tlb->start > address)
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tlb->start = address;
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if (tlb->end < address + PAGE_SIZE)
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tlb->end = address + PAGE_SIZE;
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}
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/*
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* In the case of tlb vma handling, we can optimise these away in the
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* case where we're doing a full MM flush. When we're doing a munmap,
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* the vmas are adjusted to only cover the region to be torn down.
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*/
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static inline void
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tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
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{
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if (!tlb->fullmm)
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flush_cache_range(vma, vma->vm_start, vma->vm_end);
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}
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static inline void
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tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
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{
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if (!tlb->fullmm && tlb->end) {
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flush_tlb_range(vma, tlb->start, tlb->end);
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init_tlb_gather(tlb);
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}
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}
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#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
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#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
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#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
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#define pud_free_tlb(tlb, pudp, addr) pud_free((tlb)->mm, pudp)
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#define tlb_migrate_finish(mm) do { } while (0)
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#ifdef CONFIG_CPU_SH4
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extern void tlb_wire_entry(struct vm_area_struct *, unsigned long, pte_t);
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extern void tlb_unwire_entry(void);
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#elif defined(CONFIG_SUPERH64)
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static int dtlb_entry;
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static unsigned long long dtlb_entries[64];
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static inline void tlb_wire_entry(struct vm_area_struct *vma,
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unsigned long addr, pte_t pte)
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{
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unsigned long long entry;
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unsigned long paddr, flags;
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BUG_ON(dtlb_entry == 64);
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local_irq_save(flags);
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entry = sh64_get_wired_dtlb_entry();
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dtlb_entries[dtlb_entry++] = entry;
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paddr = pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK;
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paddr &= ~PAGE_MASK;
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sh64_setup_tlb_slot(entry, addr, get_asid(), paddr);
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local_irq_restore(flags);
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}
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static inline void tlb_unwire_entry(void)
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{
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unsigned long long entry;
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unsigned long flags;
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BUG_ON(!dtlb_entry);
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local_irq_save(flags);
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entry = dtlb_entries[dtlb_entry--];
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sh64_teardown_tlb_slot(entry);
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sh64_put_wired_dtlb_entry(entry);
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local_irq_restore(flags);
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}
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#else
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static inline void tlb_wire_entry(struct vm_area_struct *vma ,
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unsigned long addr, pte_t pte)
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{
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BUG();
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}
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static inline void tlb_unwire_entry(void)
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{
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BUG();
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}
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#endif /* CONFIG_CPU_SH4 */
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#else /* CONFIG_MMU */
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0)
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#define tlb_flush(tlb) do { } while (0)
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#include <asm-generic/tlb.h>
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#endif /* CONFIG_MMU */
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_SH_TLB_H */
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