Dave Hansen 2d040a1ce9 x86/mm: New tunable for single vs full TLB flush ... Most of the logic here is in the documentation file. Please take a look at it. I know we've come full-circle here back to a tunable, but this new one is *WAY* simpler. I challenge anyone to describe in one sentence how the old one worked. Here's the way the new one works: If we are flushing more pages than the ceiling, we use the full flush, otherwise we use per-page flushes. Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Link: http://lkml.kernel.org/r/20140731154101.12B52CAF@viggo.jf.intel.com Acked-by: Rik van Riel <riel@redhat.com> Acked-by: Mel Gorman <mgorman@suse.de> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>		2014-07-31 08:48:51 -07:00
..
i386	doc: spelling error changes	2014-05-05 15:32:05 +02:00
x86_64	x86-64, espfix: Don't leak bits 31:16 of %esp returning to 16-bit stack	2014-04-30 14:14:28 -07:00
00-INDEX	Documentation/: update 00-INDEX files	2014-02-10 16:01:40 -08:00
boot.txt	x86, boot: Correct max ramdisk size name	2014-03-13 15:32:42 -07:00
early-microcode.txt	x86, microcode, amd: Early microcode patch loading support for AMD	2013-05-30 20:19:25 -07:00
earlyprintk.txt	doc: spelling error changes	2014-05-05 15:32:05 +02:00
entry_64.txt
exception-tables.txt
mtrr.txt
pat.txt
tlb.txt	x86/mm: New tunable for single vs full TLB flush	2014-07-31 08:48:51 -07:00
usb-legacy-support.txt
zero-page.txt