forked from luck/tmp_suning_uos_patched
be67c41781
This patch adds power domain indices for the RZ/G2N (a.k.a r8a774b1) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Link: https://lore.kernel.org/r/1567666326-27373-1-git-send-email-biju.das@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
27 lines
737 B
C
27 lines
737 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2019 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A774B1_PD_CA57_CPU0 0
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#define R8A774B1_PD_CA57_CPU1 1
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#define R8A774B1_PD_A3VP 9
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#define R8A774B1_PD_CA57_SCU 12
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#define R8A774B1_PD_A3VC 14
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#define R8A774B1_PD_3DG_A 17
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#define R8A774B1_PD_3DG_B 18
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#define R8A774B1_PD_A2VC1 26
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/* Always-on power area */
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#define R8A774B1_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */
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