forked from luck/tmp_suning_uos_patched
97dcb82de6
The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all
platforms and are same value on most platforms (0 or 16, depends on
CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make
them customizable. This will save a few cycle on each CPU interrupt.
A good side effect is removing some dependencies to MALTA in generic
SMTC code.
Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq
mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing
them might cause some header dependency problem and there seems no
good reason to customize it. So currently only VR41XX is using custom
MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259.
Testing this patch on those platforms is greatly appreciated. Thank
you.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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* Defines for the Malta interrupt controller.
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*
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*/
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#ifndef _MIPS_MALTAINT_H
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#define _MIPS_MALTAINT_H
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#include <irq.h>
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/*
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* Interrupts 0..15 are used for Malta ISA compatible interrupts
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*/
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#define MALTA_INT_BASE 0
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/*
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* Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode)
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*/
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#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE
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/* CPU interrupt offsets */
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#define MIPSCPU_INT_SW0 0
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#define MIPSCPU_INT_SW1 1
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#define MIPSCPU_INT_MB0 2
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#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
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#define MIPSCPU_INT_MB1 3
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#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
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#define MIPSCPU_INT_MB2 4
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#define MIPSCPU_INT_MB3 5
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#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
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#define MIPSCPU_INT_MB4 6
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#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
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#define MIPSCPU_INT_CPUCTR 7
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/*
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* Interrupts 64..127 are used for Soc-it Classic interrupts
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*/
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#define MSC01C_INT_BASE 64
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/* SOC-it Classic interrupt offsets */
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#define MSC01C_INT_TMR 0
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#define MSC01C_INT_PCI 1
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/*
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* Interrupts 64..127 are used for Soc-it EIC interrupts
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*/
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#define MSC01E_INT_BASE 64
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/* SOC-it EIC interrupt offsets */
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#define MSC01E_INT_SW0 1
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#define MSC01E_INT_SW1 2
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#define MSC01E_INT_MB0 3
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#define MSC01E_INT_I8259A MSC01E_INT_MB0
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#define MSC01E_INT_MB1 4
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#define MSC01E_INT_SMI MSC01E_INT_MB1
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#define MSC01E_INT_MB2 5
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#define MSC01E_INT_MB3 6
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#define MSC01E_INT_COREHI MSC01E_INT_MB3
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#define MSC01E_INT_MB4 7
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#define MSC01E_INT_CORELO MSC01E_INT_MB4
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#define MSC01E_INT_TMR 8
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#define MSC01E_INT_PCI 9
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#define MSC01E_INT_PERFCTR 10
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#define MSC01E_INT_CPUCTR 11
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#ifndef __ASSEMBLY__
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extern void maltaint_init(void);
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#endif
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#endif /* !(_MIPS_MALTAINT_H) */
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