Atsushi Nemoto 97dcb82de6 [MIPS] Define MIPS_CPU_IRQ_BASE in generic header ... The irq_base for {mips,rm7k,rm9k}_cpu_irq_init() are constant on all platforms and are same value on most platforms (0 or 16, depends on CONFIG_I8259). Define them in asm-mips/mach-generic/irq.h and make them customizable. This will save a few cycle on each CPU interrupt. A good side effect is removing some dependencies to MALTA in generic SMTC code. Although MIPS_CPU_IRQ_BASE is customizable, this patch changes irq mappings on DDB5477, EMMA2RH and MIPS_SIM, since really customizing them might cause some header dependency problem and there seems no good reason to customize it. So currently only VR41XX is using custom MIPS_CPU_IRQ_BASE value, which is 0 regardless of CONFIG_I8259. Testing this patch on those platforms is greatly appreciated. Thank you. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2007-02-06 16:53:08 +00:00
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gio.h	[PATCH] mips: nuke trailing whitespace	2005-09-05 00:06:07 -07:00
hpc3.h	[PATCH] sgiseeq: Configure PIO and DMA timing requests.	2005-10-18 18:03:47 -04:00
ioc.h	[PATCH] mips: nuke trailing whitespace	2005-09-05 00:06:07 -07:00
ip22.h	[MIPS] Define MIPS_CPU_IRQ_BASE in generic header	2007-02-06 16:53:08 +00:00
mc.h	[PATCH] mips: nuke trailing whitespace	2005-09-05 00:06:07 -07:00
pi1.h	Linux-2.6.12-rc2	2005-04-16 15:20:36 -07:00
sgi.h	Linux-2.6.12-rc2	2005-04-16 15:20:36 -07:00