forked from luck/tmp_suning_uos_patched
fe5720e2b7
SEC version 2.1 and above adds the capability to do the IPSec ICV memcmp in h/w. Results of the cmp are written back in the descriptor header, along with the done status. A new callback is added that checks these ICCR bits instead of performing the memcmp on the core, and is enabled by h/w capability. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> After testing on different parts, another condition was added before using h/w auth check because different SEC revisions require different handling. The SEC 3.0 allows a more flexible link table where the auth data can span separate link table entries. The SEC 2.4/2.1 does not support this case. So a test was added in the decrypt routine for a fragmented case; the h/w auth check is disallowed for revisions not having the extent in the link table; in this case the hw auth check is done by software. A portion of a previous change for SEC 3.0 link table handling was removed since it became dead code with the hw auth check supported. This seems to be the best compromise for using hw auth check on supporting SEC revisions; it keeps the link table logic simpler for the fragmented cases. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
209 lines
9.9 KiB
C
209 lines
9.9 KiB
C
/*
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* Freescale SEC (talitos) device register and descriptor header defines
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*
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* Copyright (c) 2006-2008 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
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*/
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/* global register offset addresses */
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#define TALITOS_MCR 0x1030 /* master control register */
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#define TALITOS_MCR_LO 0x1038
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#define TALITOS_MCR_SWR 0x1 /* s/w reset */
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#define TALITOS_IMR 0x1008 /* interrupt mask register */
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#define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
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#define TALITOS_IMR_DONE 0x00055 /* done IRQs */
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#define TALITOS_IMR_LO 0x100C
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#define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
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#define TALITOS_ISR 0x1010 /* interrupt status register */
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#define TALITOS_ISR_CHERR 0xaa /* channel errors mask */
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#define TALITOS_ISR_CHDONE 0x55 /* channel done mask */
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#define TALITOS_ISR_LO 0x1014
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#define TALITOS_ICR 0x1018 /* interrupt clear register */
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#define TALITOS_ICR_LO 0x101C
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/* channel register address stride */
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#define TALITOS_CH_STRIDE 0x100
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/* channel configuration register */
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#define TALITOS_CCCR(ch) (ch * TALITOS_CH_STRIDE + 0x1108)
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#define TALITOS_CCCR_CONT 0x2 /* channel continue */
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#define TALITOS_CCCR_RESET 0x1 /* channel reset */
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#define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c)
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#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
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#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
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#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
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#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
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/* CCPSR: channel pointer status register */
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#define TALITOS_CCPSR(ch) (ch * TALITOS_CH_STRIDE + 0x1110)
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#define TALITOS_CCPSR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1114)
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#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
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#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
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#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
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#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
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#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
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#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
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#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
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#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
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#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
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#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
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#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
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#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
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/* channel fetch fifo register */
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#define TALITOS_FF(ch) (ch * TALITOS_CH_STRIDE + 0x1148)
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#define TALITOS_FF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x114c)
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/* current descriptor pointer register */
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#define TALITOS_CDPR(ch) (ch * TALITOS_CH_STRIDE + 0x1140)
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#define TALITOS_CDPR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1144)
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/* descriptor buffer register */
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#define TALITOS_DESCBUF(ch) (ch * TALITOS_CH_STRIDE + 0x1180)
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#define TALITOS_DESCBUF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1184)
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/* gather link table */
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#define TALITOS_GATHER(ch) (ch * TALITOS_CH_STRIDE + 0x11c0)
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#define TALITOS_GATHER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11c4)
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/* scatter link table */
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#define TALITOS_SCATTER(ch) (ch * TALITOS_CH_STRIDE + 0x11e0)
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#define TALITOS_SCATTER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11e4)
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/* execution unit interrupt status registers */
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#define TALITOS_DEUISR 0x2030 /* DES unit */
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#define TALITOS_DEUISR_LO 0x2034
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#define TALITOS_AESUISR 0x4030 /* AES unit */
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#define TALITOS_AESUISR_LO 0x4034
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#define TALITOS_MDEUISR 0x6030 /* message digest unit */
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#define TALITOS_MDEUISR_LO 0x6034
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#define TALITOS_MDEUICR 0x6038 /* interrupt control */
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#define TALITOS_MDEUICR_LO 0x603c
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#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
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#define TALITOS_AFEUISR 0x8030 /* arc4 unit */
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#define TALITOS_AFEUISR_LO 0x8034
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#define TALITOS_RNGUISR 0xa030 /* random number unit */
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#define TALITOS_RNGUISR_LO 0xa034
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#define TALITOS_RNGUSR 0xa028 /* rng status */
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#define TALITOS_RNGUSR_LO 0xa02c
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#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
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#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
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#define TALITOS_RNGUDSR 0xa010 /* data size */
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#define TALITOS_RNGUDSR_LO 0xa014
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#define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */
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#define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */
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#define TALITOS_RNGURCR 0xa018 /* reset control */
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#define TALITOS_RNGURCR_LO 0xa01c
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#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
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#define TALITOS_PKEUISR 0xc030 /* public key unit */
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#define TALITOS_PKEUISR_LO 0xc034
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#define TALITOS_KEUISR 0xe030 /* kasumi unit */
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#define TALITOS_KEUISR_LO 0xe034
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#define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/
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#define TALITOS_CRCUISR_LO 0xf034
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/*
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* talitos descriptor header (hdr) bits
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*/
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/* written back when done */
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#define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000)
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#define DESC_HDR_LO_ICCR1_MASK __constant_cpu_to_be32(0x00180000)
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#define DESC_HDR_LO_ICCR1_PASS __constant_cpu_to_be32(0x00080000)
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#define DESC_HDR_LO_ICCR1_FAIL __constant_cpu_to_be32(0x00100000)
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/* primary execution unit select */
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#define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000)
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#define DESC_HDR_SEL0_AFEU __constant_cpu_to_be32(0x10000000)
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#define DESC_HDR_SEL0_DEU __constant_cpu_to_be32(0x20000000)
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#define DESC_HDR_SEL0_MDEUA __constant_cpu_to_be32(0x30000000)
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#define DESC_HDR_SEL0_MDEUB __constant_cpu_to_be32(0xb0000000)
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#define DESC_HDR_SEL0_RNG __constant_cpu_to_be32(0x40000000)
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#define DESC_HDR_SEL0_PKEU __constant_cpu_to_be32(0x50000000)
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#define DESC_HDR_SEL0_AESU __constant_cpu_to_be32(0x60000000)
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#define DESC_HDR_SEL0_KEU __constant_cpu_to_be32(0x70000000)
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#define DESC_HDR_SEL0_CRCU __constant_cpu_to_be32(0x80000000)
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/* primary execution unit mode (MODE0) and derivatives */
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#define DESC_HDR_MODE0_ENCRYPT __constant_cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_AESU_CBC __constant_cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_DEU_CBC __constant_cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_DEU_3DES __constant_cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_INIT __constant_cpu_to_be32(0x01000000)
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#define DESC_HDR_MODE0_MDEU_HMAC __constant_cpu_to_be32(0x00800000)
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#define DESC_HDR_MODE0_MDEU_PAD __constant_cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_MDEU_MD5 __constant_cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_SHA256 __constant_cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_MDEU_SHA1 __constant_cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
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DESC_HDR_MODE0_MDEU_HMAC)
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#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
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DESC_HDR_MODE0_MDEU_HMAC)
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#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
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DESC_HDR_MODE0_MDEU_HMAC)
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/* secondary execution unit select (SEL1) */
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#define DESC_HDR_SEL1_MASK __constant_cpu_to_be32(0x000f0000)
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#define DESC_HDR_SEL1_MDEUA __constant_cpu_to_be32(0x00030000)
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#define DESC_HDR_SEL1_MDEUB __constant_cpu_to_be32(0x000b0000)
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#define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000)
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/* secondary execution unit mode (MODE1) and derivatives */
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#define DESC_HDR_MODE1_MDEU_CICV __constant_cpu_to_be32(0x00004000)
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#define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000)
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#define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800)
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#define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400)
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#define DESC_HDR_MODE1_MDEU_MD5 __constant_cpu_to_be32(0x00000200)
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#define DESC_HDR_MODE1_MDEU_SHA256 __constant_cpu_to_be32(0x00000100)
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#define DESC_HDR_MODE1_MDEU_SHA1 __constant_cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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/* direction of overall data flow (DIR) */
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#define DESC_HDR_DIR_INBOUND __constant_cpu_to_be32(0x00000002)
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/* request done notification (DN) */
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#define DESC_HDR_DONE_NOTIFY __constant_cpu_to_be32(0x00000001)
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/* descriptor types */
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#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP __constant_cpu_to_be32(0 << 3)
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#define DESC_HDR_TYPE_IPSEC_ESP __constant_cpu_to_be32(1 << 3)
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#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU __constant_cpu_to_be32(2 << 3)
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#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU __constant_cpu_to_be32(4 << 3)
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/* link table extent field bits */
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#define DESC_PTR_LNKTBL_JUMP 0x80
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#define DESC_PTR_LNKTBL_RETURN 0x02
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#define DESC_PTR_LNKTBL_NEXT 0x01
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