forked from luck/tmp_suning_uos_patched
gpio: davinci: move to platform device
Modify DaVinci GPIO driver to become a platform device driver. The driver does not have platform driver structure or a probe. Instead, it has pure_initcall function for initialization. The platform specific informaiton is obtained using the DaVinci specific davinci_soc_info structure. This is a problem for Device Tree (DT) implementation. As a first stage of DT conversion, we implement a probe. Additional notes: - The driver registration happens as postcore_initcall. This is required since machine init functions like da850_lcd_hw_init() make use of GPIO. - Start using devres APIs for simpler error handling. Signed-off-by: KV Sujith <sujithkv@ti.com> [avinashphilip@ti.com: Move global definition of "davinci_gpio_controller" to local] Signed-off-by: Philip Avinash <avinashphilip@ti.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> [nsekhar@ti.com: drop unused structure member, rebase to new clean-up patch and fix error messages] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
This commit is contained in:
KV Sujith
Sekhar Nori
parent
131a10a395
commit
118150f22d
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@ -60,6 +60,7 @@ struct davinci_gpio_controller {
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void __iomem *set_data;
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void __iomem *clr_data;
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void __iomem *in_data;
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unsigned gpio_irq;
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};
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/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
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@ -15,8 +15,9 @@
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/gpio-davinci.h>
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struct davinci_gpio_regs {
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u32 dir;
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@ -36,10 +37,9 @@ struct davinci_gpio_regs {
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#define chip2controller(chip) \
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container_of(chip, struct davinci_gpio_controller, chip)
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static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
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static void __iomem *gpio_base;
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static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
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static struct davinci_gpio_regs __iomem *gpio2regs(unsigned gpio)
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{
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void __iomem *ptr;
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@ -67,7 +67,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
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return g;
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}
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static int __init davinci_gpio_irq_setup(void);
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static int davinci_gpio_irq_setup(struct platform_device *pdev);
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/*--------------------------------------------------------------------------*/
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@ -133,33 +133,53 @@ davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
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}
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static int __init davinci_gpio_setup(void)
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static int davinci_gpio_probe(struct platform_device *pdev)
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{
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int i, base;
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unsigned ngpio;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct davinci_gpio_regs *regs;
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struct davinci_gpio_controller *chips;
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struct davinci_gpio_platform_data *pdata;
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struct davinci_gpio_regs __iomem *regs;
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struct device *dev = &pdev->dev;
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struct resource *res;
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if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
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return 0;
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pdata = dev->platform_data;
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if (!pdata) {
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dev_err(dev, "No platform data found\n");
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return -EINVAL;
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}
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/*
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* The gpio banks conceptually expose a segmented bitmap,
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* and "ngpio" is one more than the largest zero-based
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* bit index that's valid.
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*/
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ngpio = soc_info->gpio_num;
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ngpio = pdata->ngpio;
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if (ngpio == 0) {
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pr_err("GPIO setup: how many GPIOs?\n");
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dev_err(dev, "How many GPIOs?\n");
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return -EINVAL;
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}
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if (WARN_ON(DAVINCI_N_GPIO < ngpio))
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ngpio = DAVINCI_N_GPIO;
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gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
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if (WARN_ON(!gpio_base))
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chips = devm_kzalloc(dev,
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ngpio * sizeof(struct davinci_gpio_controller),
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GFP_KERNEL);
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if (!chips) {
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dev_err(dev, "Memory allocation failed\n");
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return -ENOMEM;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev, "Invalid memory resource\n");
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return -EBUSY;
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}
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gpio_base = devm_ioremap_resource(dev, res);
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if (IS_ERR(gpio_base))
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return PTR_ERR(gpio_base);
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for (i = 0, base = 0; base < ngpio; i++, base += 32) {
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chips[i].chip.label = "DaVinci";
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@ -185,13 +205,10 @@ static int __init davinci_gpio_setup(void)
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gpiochip_add(&chips[i].chip);
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}
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soc_info->gpio_ctlrs = chips;
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soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
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davinci_gpio_irq_setup();
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platform_set_drvdata(pdev, chips);
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davinci_gpio_irq_setup(pdev);
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return 0;
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}
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pure_initcall(davinci_gpio_setup);
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/*--------------------------------------------------------------------------*/
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/*
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@ -304,14 +321,14 @@ static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
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static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct davinci_gpio_controller *d = chip2controller(chip);
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/*
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* NOTE: we assume for now that only irqs in the first gpio_chip
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* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
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*/
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if (offset < soc_info->gpio_unbanked)
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return soc_info->gpio_irq + offset;
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if (offset < d->irq_base)
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return d->gpio_irq + offset;
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else
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return -ENODEV;
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}
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@ -320,12 +337,11 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
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{
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struct davinci_gpio_controller *d;
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struct davinci_gpio_regs __iomem *g;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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u32 mask;
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d = (struct davinci_gpio_controller *)data->handler_data;
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g = (struct davinci_gpio_regs __iomem *)d->regs;
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mask = __gpio_mask(data->irq - soc_info->gpio_irq);
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mask = __gpio_mask(data->irq - d->gpio_irq);
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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@ -346,24 +362,33 @@ static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
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* (dm6446) can be set appropriately for GPIOV33 pins.
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*/
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static int __init davinci_gpio_irq_setup(void)
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static int davinci_gpio_irq_setup(struct platform_device *pdev)
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{
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unsigned gpio, irq, bank;
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struct clk *clk;
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u32 binten = 0;
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unsigned ngpio, bank_irq;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct davinci_gpio_regs __iomem *g;
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
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struct davinci_gpio_platform_data *pdata = dev->platform_data;
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struct davinci_gpio_regs __iomem *g;
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ngpio = soc_info->gpio_num;
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bank_irq = soc_info->gpio_irq;
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if (bank_irq == 0) {
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printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
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return -EINVAL;
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ngpio = pdata->ngpio;
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res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!res) {
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dev_err(dev, "Invalid IRQ resource\n");
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return -EBUSY;
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}
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clk = clk_get(NULL, "gpio");
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bank_irq = res->start;
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if (!bank_irq) {
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dev_err(dev, "Invalid IRQ resource\n");
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return -ENODEV;
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}
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clk = devm_clk_get(dev, "gpio");
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if (IS_ERR(clk)) {
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printk(KERN_ERR "Error %ld getting gpio clock?\n",
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PTR_ERR(clk));
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@ -379,9 +404,9 @@ static int __init davinci_gpio_irq_setup(void)
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*/
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for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
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chips[bank].chip.to_irq = gpio_to_irq_banked;
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chips[bank].irq_base = soc_info->gpio_unbanked
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chips[bank].irq_base = pdata->gpio_unbanked
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? -EINVAL
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: (soc_info->intc_irq_num + gpio);
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: (pdata->intc_irq_num + gpio);
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}
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/*
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@ -389,7 +414,7 @@ static int __init davinci_gpio_irq_setup(void)
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* controller only handling trigger modes. We currently assume no
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* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
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*/
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if (soc_info->gpio_unbanked) {
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if (pdata->gpio_unbanked) {
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static struct irq_chip_type gpio_unbanked;
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/* pass "bank 0" GPIO IRQs to AINTC */
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@ -409,7 +434,7 @@ static int __init davinci_gpio_irq_setup(void)
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__raw_writel(~0, &g->set_rising);
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/* set the direct IRQs up to use that irqchip */
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for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
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for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
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irq_set_chip(irq, &gpio_unbanked.chip);
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irq_set_handler_data(irq, &chips[gpio / 32]);
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irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
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@ -464,3 +489,21 @@ static int __init davinci_gpio_irq_setup(void)
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return 0;
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}
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static struct platform_driver davinci_gpio_driver = {
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.probe = davinci_gpio_probe,
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.driver = {
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.name = "davinci_gpio",
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.owner = THIS_MODULE,
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},
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};
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/**
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* GPIO driver registration needs to be done before machine_init functions
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* access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
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*/
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static int __init davinci_gpio_drv_reg(void)
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{
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return platform_driver_register(&davinci_gpio_driver);
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}
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postcore_initcall(davinci_gpio_drv_reg);
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25
include/linux/platform_data/gpio-davinci.h
Normal file
25
include/linux/platform_data/gpio-davinci.h
Normal file
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@ -0,0 +1,25 @@
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/*
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* DaVinci GPIO Platform Related Defines
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_GPIO_PLATFORM_H
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#define __DAVINCI_GPIO_PLATFORM_H
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struct davinci_gpio_platform_data {
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u32 ngpio;
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u32 gpio_unbanked;
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u32 intc_irq_num;
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};
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#endif
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