forked from luck/tmp_suning_uos_patched
irqchip/loongson-pch-pic: Fix the misused irq flow handler
Loongson PCH PIC is a standard level triggered PIC, and it need to clear
interrupt during unmask.
Fixes: ef8c01eb64
("irqchip: Add Loongson PCH PIC controller")
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Link: https://lore.kernel.org/r/1596099090-23516-6-git-send-email-chenhc@lemote.com
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c47e388cfc
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ac62460c24
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@ -64,15 +64,6 @@ static void pch_pic_bitclr(struct pch_pic *priv, int offset, int bit)
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raw_spin_unlock(&priv->pic_lock);
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}
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static void pch_pic_eoi_irq(struct irq_data *d)
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{
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u32 idx = PIC_REG_IDX(d->hwirq);
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struct pch_pic *priv = irq_data_get_irq_chip_data(d);
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writel(BIT(PIC_REG_BIT(d->hwirq)),
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priv->base + PCH_PIC_CLR + idx * 4);
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}
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static void pch_pic_mask_irq(struct irq_data *d)
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{
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struct pch_pic *priv = irq_data_get_irq_chip_data(d);
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@ -85,6 +76,9 @@ static void pch_pic_unmask_irq(struct irq_data *d)
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{
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struct pch_pic *priv = irq_data_get_irq_chip_data(d);
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writel(BIT(PIC_REG_BIT(d->hwirq)),
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priv->base + PCH_PIC_CLR + PIC_REG_IDX(d->hwirq) * 4);
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irq_chip_unmask_parent(d);
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pch_pic_bitclr(priv, PCH_PIC_MASK, d->hwirq);
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}
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@ -124,7 +118,6 @@ static struct irq_chip pch_pic_irq_chip = {
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.irq_mask = pch_pic_mask_irq,
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.irq_unmask = pch_pic_unmask_irq,
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.irq_ack = irq_chip_ack_parent,
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.irq_eoi = pch_pic_eoi_irq,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.irq_set_type = pch_pic_set_type,
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};
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@ -153,7 +146,7 @@ static int pch_pic_alloc(struct irq_domain *domain, unsigned int virq,
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irq_domain_set_info(domain, virq, hwirq,
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&pch_pic_irq_chip, priv,
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handle_fasteoi_ack_irq, NULL, NULL);
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handle_level_irq, NULL, NULL);
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irq_set_probe(virq);
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return 0;
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