forked from luck/tmp_suning_uos_patched
arm64: tegra: Changes for v5.10-rc1
This set of changes fixes some minor issues in existing device trees and adds ID EEPROMs on the Jetson Xavier NX. All ID EEPROMs are now labelled to allow them to be detected by software. It also adds support for the Tegra234 VDK board, which is a pre-silicon platform for the upcoming Orin SoC. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl9ky48THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoVVtEACJcW6ztbQiqrksFdVW+8wlT/EZwNwr qwwjGvy0ovJIYAPTB+XhGllUp17QR2EVzdGJW9Q8mr92QRpoQxSg3yB3BaJWsMoz AH+9qkQoRE5F+aFwO2l8kTBDswyiOQCLxsiDSCcCWTHtvAQOl/K2HjG+4kxtko+C 0in+p67PG0t4qanjeTApWEWXjfiXBpM0bcv89TKK0SO+k+zsjupEZeOnVIbEpGTa SMjKm/0l0jZIEMoweqX3H0jpTBvqE6IjLm4EAbCfLJrhDEIQe50WkNpw2CVaCZy6 2Mjnv7Gr/XO3MKmM4stLYTZ9eu5qDa7wGrQT/mXZt7kEc3L85rGZGyWQm5bCmspa mSKZ+swtegkEBBofOabxcCDi0V9KxDiba3hwv4mr17qMjj7VBK5le3JhUS19qnZ8 Osu81JqKrDjfkmxtqSnJEeTTVwxBG09WQ5lME9FRBqH9P5Y1L7yCAuqPLzYhXxtj KAcqveVzoMMi2YIp4Rt07seWsHhuNqkY9XWtPWrgubGtU1AKYXWHYDojefyo1VUq 1bOkzSa+ZVBwZuRmdgn2vxbeJnexeTAPolJp4WCpJpSGJbiFKNqhh5scjjfSviGS PfOITtuJgaxoqEZRhCdF/VM2+YSjjVljRkiE6b8W0+eKkeQKzzDvJIDnOqeb7PGX 1gJniuIR25eShg== =zeT7 -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.10-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Changes for v5.10-rc1 This set of changes fixes some minor issues in existing device trees and adds ID EEPROMs on the Jetson Xavier NX. All ID EEPROMs are now labelled to allow them to be detected by software. It also adds support for the Tegra234 VDK board, which is a pre-silicon platform for the upcoming Orin SoC. * tag 'tegra-for-5.10-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Initial Tegra234 VDK support arm64: tegra: Populate EEPROMs for Jetson Xavier NX arm64: tegra: Add label properties for EEPROMs arm64: tegra: Add DT binding for AHUB components arm64: tegra: Enable ACONNECT, ADMA and AGIC on Jetson Nano arm64: tegra: Properly size register regions for GPU on Tegra194 arm64: tegra: Use valid PWM period for VDD_GPU on Tegra210 arm64: tegra: Describe display controller outputs for Tegra210 arm64: tegra: Disable SD card write-protection on Jetson Nano arm64: tegra: Add VBUS supply for micro USB port on Jetson Nano arm64: tegra: Wire up pinctrl states for all DPAUX controllers arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier Link: https://lore.kernel.org/r/20200918150303.3938852-5-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
dd59aed76d
|
|
@ -9,3 +9,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb
|
||||||
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
|
dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb
|
||||||
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
|
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb
|
||||||
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
|
dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb
|
||||||
|
dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb
|
||||||
|
|
|
||||||
|
|
@ -222,6 +222,7 @@ eeprom@57 {
|
||||||
compatible = "atmel,24c02";
|
compatible = "atmel,24c02";
|
||||||
reg = <0x57>;
|
reg = <0x57>;
|
||||||
|
|
||||||
|
label = "system";
|
||||||
vcc-supply = <&vdd_1v8>;
|
vcc-supply = <&vdd_1v8>;
|
||||||
address-width = <8>;
|
address-width = <8>;
|
||||||
pagesize = <8>;
|
pagesize = <8>;
|
||||||
|
|
|
||||||
|
|
@ -173,6 +173,7 @@ eeprom@50 {
|
||||||
compatible = "atmel,24c02";
|
compatible = "atmel,24c02";
|
||||||
reg = <0x50>;
|
reg = <0x50>;
|
||||||
|
|
||||||
|
label = "module";
|
||||||
vcc-supply = <&vdd_1v8>;
|
vcc-supply = <&vdd_1v8>;
|
||||||
address-width = <8>;
|
address-width = <8>;
|
||||||
pagesize = <8>;
|
pagesize = <8>;
|
||||||
|
|
|
||||||
|
|
@ -85,7 +85,7 @@ aconnect {
|
||||||
ranges = <0x02900000 0x0 0x02900000 0x200000>;
|
ranges = <0x02900000 0x0 0x02900000 0x200000>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
dma-controller@2930000 {
|
adma: dma-controller@2930000 {
|
||||||
compatible = "nvidia,tegra186-adma";
|
compatible = "nvidia,tegra186-adma";
|
||||||
reg = <0x02930000 0x20000>;
|
reg = <0x02930000 0x20000>;
|
||||||
interrupt-parent = <&agic>;
|
interrupt-parent = <&agic>;
|
||||||
|
|
@ -140,6 +140,221 @@ agic: interrupt-controller@2a40000 {
|
||||||
clock-names = "clk";
|
clock-names = "clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
tegra_ahub: ahub@2900800 {
|
||||||
|
compatible = "nvidia,tegra186-ahub";
|
||||||
|
reg = <0x02900800 0x800>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_AHUB>;
|
||||||
|
clock-names = "ahub";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x02900800 0x02900800 0x11800>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
tegra_admaif: admaif@290f000 {
|
||||||
|
compatible = "nvidia,tegra186-admaif";
|
||||||
|
reg = <0x0290f000 0x1000>;
|
||||||
|
dmas = <&adma 1>, <&adma 1>,
|
||||||
|
<&adma 2>, <&adma 2>,
|
||||||
|
<&adma 3>, <&adma 3>,
|
||||||
|
<&adma 4>, <&adma 4>,
|
||||||
|
<&adma 5>, <&adma 5>,
|
||||||
|
<&adma 6>, <&adma 6>,
|
||||||
|
<&adma 7>, <&adma 7>,
|
||||||
|
<&adma 8>, <&adma 8>,
|
||||||
|
<&adma 9>, <&adma 9>,
|
||||||
|
<&adma 10>, <&adma 10>,
|
||||||
|
<&adma 11>, <&adma 11>,
|
||||||
|
<&adma 12>, <&adma 12>,
|
||||||
|
<&adma 13>, <&adma 13>,
|
||||||
|
<&adma 14>, <&adma 14>,
|
||||||
|
<&adma 15>, <&adma 15>,
|
||||||
|
<&adma 16>, <&adma 16>,
|
||||||
|
<&adma 17>, <&adma 17>,
|
||||||
|
<&adma 18>, <&adma 18>,
|
||||||
|
<&adma 19>, <&adma 19>,
|
||||||
|
<&adma 20>, <&adma 20>;
|
||||||
|
dma-names = "rx1", "tx1",
|
||||||
|
"rx2", "tx2",
|
||||||
|
"rx3", "tx3",
|
||||||
|
"rx4", "tx4",
|
||||||
|
"rx5", "tx5",
|
||||||
|
"rx6", "tx6",
|
||||||
|
"rx7", "tx7",
|
||||||
|
"rx8", "tx8",
|
||||||
|
"rx9", "tx9",
|
||||||
|
"rx10", "tx10",
|
||||||
|
"rx11", "tx11",
|
||||||
|
"rx12", "tx12",
|
||||||
|
"rx13", "tx13",
|
||||||
|
"rx14", "tx14",
|
||||||
|
"rx15", "tx15",
|
||||||
|
"rx16", "tx16",
|
||||||
|
"rx17", "tx17",
|
||||||
|
"rx18", "tx18",
|
||||||
|
"rx19", "tx19",
|
||||||
|
"rx20", "tx20";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s1: i2s@2901000 {
|
||||||
|
compatible = "nvidia,tegra186-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901000 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_I2S1>,
|
||||||
|
<&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s2: i2s@2901100 {
|
||||||
|
compatible = "nvidia,tegra186-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901100 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_I2S2>,
|
||||||
|
<&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s3: i2s@2901200 {
|
||||||
|
compatible = "nvidia,tegra186-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901200 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_I2S3>,
|
||||||
|
<&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S3";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s4: i2s@2901300 {
|
||||||
|
compatible = "nvidia,tegra186-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901300 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_I2S4>,
|
||||||
|
<&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S4";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s5: i2s@2901400 {
|
||||||
|
compatible = "nvidia,tegra186-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901400 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_I2S5>,
|
||||||
|
<&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S5";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s6: i2s@2901500 {
|
||||||
|
compatible = "nvidia,tegra186-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901500 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_I2S6>,
|
||||||
|
<&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S6";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic1: dmic@2904000 {
|
||||||
|
compatible = "nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904000 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_DMIC1>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic2: dmic@2904100 {
|
||||||
|
compatible = "nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904100 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_DMIC2>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic3: dmic@2904200 {
|
||||||
|
compatible = "nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904200 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_DMIC3>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC3";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic4: dmic@2904300 {
|
||||||
|
compatible = "nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904300 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_DMIC4>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC4";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dspk1: dspk@2905000 {
|
||||||
|
compatible = "nvidia,tegra186-dspk";
|
||||||
|
reg = <0x2905000 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_DSPK1>;
|
||||||
|
clock-names = "dspk";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <12288000>;
|
||||||
|
sound-name-prefix = "DSPK1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dspk2: dspk@2905100 {
|
||||||
|
compatible = "nvidia,tegra186-dspk";
|
||||||
|
reg = <0x2905100 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA186_CLK_DSPK2>;
|
||||||
|
clock-names = "dspk";
|
||||||
|
assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <12288000>;
|
||||||
|
sound-name-prefix = "DSPK2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
mc: memory-controller@2c00000 {
|
mc: memory-controller@2c00000 {
|
||||||
|
|
|
||||||
|
|
@ -57,6 +57,22 @@ serial@3110000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
i2c@3160000 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
eeprom@50 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x50>;
|
||||||
|
|
||||||
|
label = "module";
|
||||||
|
vcc-supply = <&vdd_1v8ls>;
|
||||||
|
address-width = <8>;
|
||||||
|
pagesize = <8>;
|
||||||
|
size = <256>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
/* SDMMC1 (SD/MMC) */
|
/* SDMMC1 (SD/MMC) */
|
||||||
mmc@3400000 {
|
mmc@3400000 {
|
||||||
cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;
|
cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>;
|
||||||
|
|
|
||||||
|
|
@ -23,6 +23,20 @@ interrupt-controller@2a40000 {
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
i2c@3160000 {
|
||||||
|
eeprom@56 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x56>;
|
||||||
|
|
||||||
|
label = "system";
|
||||||
|
vcc-supply = <&vdd_1v8ls>;
|
||||||
|
address-width = <8>;
|
||||||
|
pagesize = <8>;
|
||||||
|
size = <256>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
ddc: i2c@31c0000 {
|
ddc: i2c@31c0000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -27,6 +27,20 @@ ddc: i2c@3190000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
i2c@3160000 {
|
||||||
|
eeprom@57 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x57>;
|
||||||
|
|
||||||
|
label = "system";
|
||||||
|
vcc-supply = <&vdd_1v8>;
|
||||||
|
address-width = <8>;
|
||||||
|
pagesize = <8>;
|
||||||
|
size = <256>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
hda@3510000 {
|
hda@3510000 {
|
||||||
nvidia,model = "jetson-xavier-nx-hda";
|
nvidia,model = "jetson-xavier-nx-hda";
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
|
||||||
|
|
@ -58,6 +58,22 @@ serial@c280000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
i2c@3160000 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
eeprom@50 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x50>;
|
||||||
|
|
||||||
|
label = "module";
|
||||||
|
vcc-supply = <&vdd_1v8ls>;
|
||||||
|
address-width = <8>;
|
||||||
|
pagesize = <8>;
|
||||||
|
size = <256>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
/* SDMMC1 (SD/MMC) */
|
/* SDMMC1 (SD/MMC) */
|
||||||
mmc@3400000 {
|
mmc@3400000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
|
||||||
|
|
@ -83,7 +83,7 @@ aconnect@2900000 {
|
||||||
ranges = <0x02900000 0x02900000 0x200000>;
|
ranges = <0x02900000 0x02900000 0x200000>;
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
||||||
dma-controller@2930000 {
|
adma: dma-controller@2930000 {
|
||||||
compatible = "nvidia,tegra194-adma",
|
compatible = "nvidia,tegra194-adma",
|
||||||
"nvidia,tegra186-adma";
|
"nvidia,tegra186-adma";
|
||||||
reg = <0x02930000 0x20000>;
|
reg = <0x02930000 0x20000>;
|
||||||
|
|
@ -140,6 +140,229 @@ agic: interrupt-controller@2a40000 {
|
||||||
clock-names = "clk";
|
clock-names = "clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
tegra_ahub: ahub@2900800 {
|
||||||
|
compatible = "nvidia,tegra194-ahub",
|
||||||
|
"nvidia,tegra186-ahub";
|
||||||
|
reg = <0x02900800 0x800>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_AHUB>;
|
||||||
|
clock-names = "ahub";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x02900800 0x02900800 0x11800>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
tegra_admaif: admaif@290f000 {
|
||||||
|
compatible = "nvidia,tegra194-admaif",
|
||||||
|
"nvidia,tegra186-admaif";
|
||||||
|
reg = <0x0290f000 0x1000>;
|
||||||
|
dmas = <&adma 1>, <&adma 1>,
|
||||||
|
<&adma 2>, <&adma 2>,
|
||||||
|
<&adma 3>, <&adma 3>,
|
||||||
|
<&adma 4>, <&adma 4>,
|
||||||
|
<&adma 5>, <&adma 5>,
|
||||||
|
<&adma 6>, <&adma 6>,
|
||||||
|
<&adma 7>, <&adma 7>,
|
||||||
|
<&adma 8>, <&adma 8>,
|
||||||
|
<&adma 9>, <&adma 9>,
|
||||||
|
<&adma 10>, <&adma 10>,
|
||||||
|
<&adma 11>, <&adma 11>,
|
||||||
|
<&adma 12>, <&adma 12>,
|
||||||
|
<&adma 13>, <&adma 13>,
|
||||||
|
<&adma 14>, <&adma 14>,
|
||||||
|
<&adma 15>, <&adma 15>,
|
||||||
|
<&adma 16>, <&adma 16>,
|
||||||
|
<&adma 17>, <&adma 17>,
|
||||||
|
<&adma 18>, <&adma 18>,
|
||||||
|
<&adma 19>, <&adma 19>,
|
||||||
|
<&adma 20>, <&adma 20>;
|
||||||
|
dma-names = "rx1", "tx1",
|
||||||
|
"rx2", "tx2",
|
||||||
|
"rx3", "tx3",
|
||||||
|
"rx4", "tx4",
|
||||||
|
"rx5", "tx5",
|
||||||
|
"rx6", "tx6",
|
||||||
|
"rx7", "tx7",
|
||||||
|
"rx8", "tx8",
|
||||||
|
"rx9", "tx9",
|
||||||
|
"rx10", "tx10",
|
||||||
|
"rx11", "tx11",
|
||||||
|
"rx12", "tx12",
|
||||||
|
"rx13", "tx13",
|
||||||
|
"rx14", "tx14",
|
||||||
|
"rx15", "tx15",
|
||||||
|
"rx16", "tx16",
|
||||||
|
"rx17", "tx17",
|
||||||
|
"rx18", "tx18",
|
||||||
|
"rx19", "tx19",
|
||||||
|
"rx20", "tx20";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s1: i2s@2901000 {
|
||||||
|
compatible = "nvidia,tegra194-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901000 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_I2S1>,
|
||||||
|
<&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s2: i2s@2901100 {
|
||||||
|
compatible = "nvidia,tegra194-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901100 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_I2S2>,
|
||||||
|
<&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s3: i2s@2901200 {
|
||||||
|
compatible = "nvidia,tegra194-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901200 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_I2S3>,
|
||||||
|
<&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S3";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s4: i2s@2901300 {
|
||||||
|
compatible = "nvidia,tegra194-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901300 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_I2S4>,
|
||||||
|
<&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S4";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s5: i2s@2901400 {
|
||||||
|
compatible = "nvidia,tegra194-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901400 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_I2S5>,
|
||||||
|
<&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S5";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s6: i2s@2901500 {
|
||||||
|
compatible = "nvidia,tegra194-i2s",
|
||||||
|
"nvidia,tegra210-i2s";
|
||||||
|
reg = <0x2901500 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_I2S6>,
|
||||||
|
<&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S6";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic1: dmic@2904000 {
|
||||||
|
compatible = "nvidia,tegra194-dmic",
|
||||||
|
"nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904000 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_DMIC1>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic2: dmic@2904100 {
|
||||||
|
compatible = "nvidia,tegra194-dmic",
|
||||||
|
"nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904100 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_DMIC2>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic3: dmic@2904200 {
|
||||||
|
compatible = "nvidia,tegra194-dmic",
|
||||||
|
"nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904200 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_DMIC3>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC3";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic4: dmic@2904300 {
|
||||||
|
compatible = "nvidia,tegra194-dmic",
|
||||||
|
"nvidia,tegra210-dmic";
|
||||||
|
reg = <0x2904300 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_DMIC4>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC4";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dspk1: dspk@2905000 {
|
||||||
|
compatible = "nvidia,tegra194-dspk",
|
||||||
|
"nvidia,tegra186-dspk";
|
||||||
|
reg = <0x2905000 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_DSPK1>;
|
||||||
|
clock-names = "dspk";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <12288000>;
|
||||||
|
sound-name-prefix = "DSPK1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dspk2: dspk@2905100 {
|
||||||
|
compatible = "nvidia,tegra194-dspk",
|
||||||
|
"nvidia,tegra186-dspk";
|
||||||
|
reg = <0x2905100 0x100>;
|
||||||
|
clocks = <&bpmp TEGRA194_CLK_DSPK2>;
|
||||||
|
clock-names = "dspk";
|
||||||
|
assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>;
|
||||||
|
assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>;
|
||||||
|
assigned-clock-rates = <12288000>;
|
||||||
|
sound-name-prefix = "DSPK2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
pinmux: pinmux@2430000 {
|
pinmux: pinmux@2430000 {
|
||||||
|
|
@ -329,6 +552,9 @@ dp_aux_ch1_i2c: i2c@3190000 {
|
||||||
clock-names = "div-clk";
|
clock-names = "div-clk";
|
||||||
resets = <&bpmp TEGRA194_RESET_I2C4>;
|
resets = <&bpmp TEGRA194_RESET_I2C4>;
|
||||||
reset-names = "i2c";
|
reset-names = "i2c";
|
||||||
|
pinctrl-0 = <&state_dpaux1_i2c>;
|
||||||
|
pinctrl-1 = <&state_dpaux1_off>;
|
||||||
|
pinctrl-names = "default", "idle";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -343,10 +569,14 @@ dp_aux_ch0_i2c: i2c@31b0000 {
|
||||||
clock-names = "div-clk";
|
clock-names = "div-clk";
|
||||||
resets = <&bpmp TEGRA194_RESET_I2C6>;
|
resets = <&bpmp TEGRA194_RESET_I2C6>;
|
||||||
reset-names = "i2c";
|
reset-names = "i2c";
|
||||||
|
pinctrl-0 = <&state_dpaux0_i2c>;
|
||||||
|
pinctrl-1 = <&state_dpaux0_off>;
|
||||||
|
pinctrl-names = "default", "idle";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
gen7_i2c: i2c@31c0000 {
|
/* shares pads with dpaux2 */
|
||||||
|
dp_aux_ch2_i2c: i2c@31c0000 {
|
||||||
compatible = "nvidia,tegra194-i2c";
|
compatible = "nvidia,tegra194-i2c";
|
||||||
reg = <0x031c0000 0x10000>;
|
reg = <0x031c0000 0x10000>;
|
||||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
@ -356,10 +586,14 @@ gen7_i2c: i2c@31c0000 {
|
||||||
clock-names = "div-clk";
|
clock-names = "div-clk";
|
||||||
resets = <&bpmp TEGRA194_RESET_I2C7>;
|
resets = <&bpmp TEGRA194_RESET_I2C7>;
|
||||||
reset-names = "i2c";
|
reset-names = "i2c";
|
||||||
|
pinctrl-0 = <&state_dpaux2_i2c>;
|
||||||
|
pinctrl-1 = <&state_dpaux2_off>;
|
||||||
|
pinctrl-names = "default", "idle";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
gen9_i2c: i2c@31e0000 {
|
/* shares pads with dpaux3 */
|
||||||
|
dp_aux_ch3_i2c: i2c@31e0000 {
|
||||||
compatible = "nvidia,tegra194-i2c";
|
compatible = "nvidia,tegra194-i2c";
|
||||||
reg = <0x031e0000 0x10000>;
|
reg = <0x031e0000 0x10000>;
|
||||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
@ -369,6 +603,9 @@ gen9_i2c: i2c@31e0000 {
|
||||||
clock-names = "div-clk";
|
clock-names = "div-clk";
|
||||||
resets = <&bpmp TEGRA194_RESET_I2C9>;
|
resets = <&bpmp TEGRA194_RESET_I2C9>;
|
||||||
reset-names = "i2c";
|
reset-names = "i2c";
|
||||||
|
pinctrl-0 = <&state_dpaux3_i2c>;
|
||||||
|
pinctrl-1 = <&state_dpaux3_off>;
|
||||||
|
pinctrl-names = "default", "idle";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -1398,8 +1635,8 @@ sor3: sor@15bc0000 {
|
||||||
|
|
||||||
gpu@17000000 {
|
gpu@17000000 {
|
||||||
compatible = "nvidia,gv11b";
|
compatible = "nvidia,gv11b";
|
||||||
reg = <0x17000000 0x10000000>,
|
reg = <0x17000000 0x1000000>,
|
||||||
<0x18000000 0x10000000>;
|
<0x18000000 0x1000000>;
|
||||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
interrupt-names = "stall", "nonstall";
|
interrupt-names = "stall", "nonstall";
|
||||||
|
|
|
||||||
|
|
@ -273,6 +273,7 @@ eeprom@50 {
|
||||||
compatible = "atmel,24c02";
|
compatible = "atmel,24c02";
|
||||||
reg = <0x50>;
|
reg = <0x50>;
|
||||||
|
|
||||||
|
label = "module";
|
||||||
vcc-supply = <&vdd_1v8>;
|
vcc-supply = <&vdd_1v8>;
|
||||||
address-width = <8>;
|
address-width = <8>;
|
||||||
pagesize = <8>;
|
pagesize = <8>;
|
||||||
|
|
@ -337,7 +338,7 @@ psci {
|
||||||
|
|
||||||
vdd_gpu: regulator@100 {
|
vdd_gpu: regulator@100 {
|
||||||
compatible = "pwm-regulator";
|
compatible = "pwm-regulator";
|
||||||
pwms = <&pwm 1 4880>;
|
pwms = <&pwm 1 8000>;
|
||||||
regulator-name = "VDD_GPU";
|
regulator-name = "VDD_GPU";
|
||||||
regulator-min-microvolt = <710000>;
|
regulator-min-microvolt = <710000>;
|
||||||
regulator-max-microvolt = <1320000>;
|
regulator-max-microvolt = <1320000>;
|
||||||
|
|
|
||||||
|
|
@ -86,6 +86,7 @@ eeprom@57 {
|
||||||
compatible = "atmel,24c02";
|
compatible = "atmel,24c02";
|
||||||
reg = <0x57>;
|
reg = <0x57>;
|
||||||
|
|
||||||
|
label = "system";
|
||||||
vcc-supply = <&vdd_1v8>;
|
vcc-supply = <&vdd_1v8>;
|
||||||
address-width = <8>;
|
address-width = <8>;
|
||||||
pagesize = <8>;
|
pagesize = <8>;
|
||||||
|
|
|
||||||
|
|
@ -144,6 +144,7 @@ eeprom@50 {
|
||||||
compatible = "atmel,24c02";
|
compatible = "atmel,24c02";
|
||||||
reg = <0x50>;
|
reg = <0x50>;
|
||||||
|
|
||||||
|
label = "module";
|
||||||
vcc-supply = <&vdd_1v8>;
|
vcc-supply = <&vdd_1v8>;
|
||||||
address-width = <8>;
|
address-width = <8>;
|
||||||
pagesize = <8>;
|
pagesize = <8>;
|
||||||
|
|
@ -155,6 +156,7 @@ eeprom@57 {
|
||||||
compatible = "atmel,24c02";
|
compatible = "atmel,24c02";
|
||||||
reg = <0x57>;
|
reg = <0x57>;
|
||||||
|
|
||||||
|
label = "system";
|
||||||
vcc-supply = <&vdd_1v8>;
|
vcc-supply = <&vdd_1v8>;
|
||||||
address-width = <8>;
|
address-width = <8>;
|
||||||
pagesize = <8>;
|
pagesize = <8>;
|
||||||
|
|
@ -541,6 +543,8 @@ usb2-0 {
|
||||||
mode = "peripheral";
|
mode = "peripheral";
|
||||||
usb-role-switch;
|
usb-role-switch;
|
||||||
|
|
||||||
|
vbus-supply = <&vdd_5v0_usb>;
|
||||||
|
|
||||||
connector {
|
connector {
|
||||||
compatible = "gpio-usb-b-connector",
|
compatible = "gpio-usb-b-connector",
|
||||||
"usb-b-connector";
|
"usb-b-connector";
|
||||||
|
|
@ -574,6 +578,7 @@ mmc@700b0000 {
|
||||||
bus-width = <4>;
|
bus-width = <4>;
|
||||||
|
|
||||||
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
|
cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
|
||||||
|
disable-wp;
|
||||||
|
|
||||||
vqmmc-supply = <&vddio_sdmmc>;
|
vqmmc-supply = <&vddio_sdmmc>;
|
||||||
vmmc-supply = <&vdd_3v3_sd>;
|
vmmc-supply = <&vdd_3v3_sd>;
|
||||||
|
|
@ -621,6 +626,18 @@ clock@70110000 {
|
||||||
pinctrl-1 = <&dvfs_pwm_inactive_state>;
|
pinctrl-1 = <&dvfs_pwm_inactive_state>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
aconnect@702c0000 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
dma@702e2000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
interrupt-controller@702f9000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
clk32k_in: clock@0 {
|
clk32k_in: clock@0 {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
|
|
@ -818,7 +835,7 @@ vdd_cpu: regulator@5 {
|
||||||
|
|
||||||
vdd_gpu: regulator@6 {
|
vdd_gpu: regulator@6 {
|
||||||
compatible = "pwm-regulator";
|
compatible = "pwm-regulator";
|
||||||
pwms = <&pwm 1 4880>;
|
pwms = <&pwm 1 8000>;
|
||||||
|
|
||||||
regulator-name = "VDD_GPU";
|
regulator-name = "VDD_GPU";
|
||||||
regulator-min-microvolt = <710000>;
|
regulator-min-microvolt = <710000>;
|
||||||
|
|
@ -843,4 +860,14 @@ avdd_io_edp_1v05: regulator@7 {
|
||||||
|
|
||||||
vin-supply = <&avdd_1v05_pll>;
|
vin-supply = <&avdd_1v05_pll>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
vdd_5v0_usb: regulator@8 {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
|
||||||
|
regulator-name = "VDD_5V_USB";
|
||||||
|
regulator-min-microvolt = <50000000>;
|
||||||
|
regulator-max-microvolt = <50000000>;
|
||||||
|
|
||||||
|
vin-supply = <&vdd_5v0_sys>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -194,6 +194,7 @@ dc@54200000 {
|
||||||
|
|
||||||
iommus = <&mc TEGRA_SWGROUP_DC>;
|
iommus = <&mc TEGRA_SWGROUP_DC>;
|
||||||
|
|
||||||
|
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
|
||||||
nvidia,head = <0>;
|
nvidia,head = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
@ -208,10 +209,11 @@ dc@54240000 {
|
||||||
|
|
||||||
iommus = <&mc TEGRA_SWGROUP_DCB>;
|
iommus = <&mc TEGRA_SWGROUP_DCB>;
|
||||||
|
|
||||||
|
nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
|
||||||
nvidia,head = <1>;
|
nvidia,head = <1>;
|
||||||
};
|
};
|
||||||
|
|
||||||
dsi@54300000 {
|
dsia: dsi@54300000 {
|
||||||
compatible = "nvidia,tegra210-dsi";
|
compatible = "nvidia,tegra210-dsi";
|
||||||
reg = <0x0 0x54300000 0x0 0x00040000>;
|
reg = <0x0 0x54300000 0x0 0x00040000>;
|
||||||
clocks = <&tegra_car TEGRA210_CLK_DSIA>,
|
clocks = <&tegra_car TEGRA210_CLK_DSIA>,
|
||||||
|
|
@ -248,7 +250,7 @@ nvjpg@54380000 {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
dsi@54400000 {
|
dsib: dsi@54400000 {
|
||||||
compatible = "nvidia,tegra210-dsi";
|
compatible = "nvidia,tegra210-dsi";
|
||||||
reg = <0x0 0x54400000 0x0 0x00040000>;
|
reg = <0x0 0x54400000 0x0 0x00040000>;
|
||||||
clocks = <&tegra_car TEGRA210_CLK_DSIB>,
|
clocks = <&tegra_car TEGRA210_CLK_DSIB>,
|
||||||
|
|
@ -284,7 +286,7 @@ tsec@54500000 {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
sor@54540000 {
|
sor0: sor@54540000 {
|
||||||
compatible = "nvidia,tegra210-sor";
|
compatible = "nvidia,tegra210-sor";
|
||||||
reg = <0x0 0x54540000 0x0 0x00040000>;
|
reg = <0x0 0x54540000 0x0 0x00040000>;
|
||||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
@ -304,7 +306,7 @@ sor@54540000 {
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
sor@54580000 {
|
sor1: sor@54580000 {
|
||||||
compatible = "nvidia,tegra210-sor1";
|
compatible = "nvidia,tegra210-sor1";
|
||||||
reg = <0x0 0x54580000 0x0 0x00040000>;
|
reg = <0x0 0x54580000 0x0 0x00040000>;
|
||||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
|
@ -1381,6 +1383,146 @@ agic: interrupt-controller@702f9000 {
|
||||||
clock-names = "clk";
|
clock-names = "clk";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
tegra_ahub: ahub@702d0800 {
|
||||||
|
compatible = "nvidia,tegra210-ahub";
|
||||||
|
reg = <0x702d0800 0x800>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
|
||||||
|
clock-names = "ahub";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x702d0000 0x702d0000 0x0000e400>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
tegra_admaif: admaif@702d0000 {
|
||||||
|
compatible = "nvidia,tegra210-admaif";
|
||||||
|
reg = <0x702d0000 0x800>;
|
||||||
|
dmas = <&adma 1>, <&adma 1>,
|
||||||
|
<&adma 2>, <&adma 2>,
|
||||||
|
<&adma 3>, <&adma 3>,
|
||||||
|
<&adma 4>, <&adma 4>,
|
||||||
|
<&adma 5>, <&adma 5>,
|
||||||
|
<&adma 6>, <&adma 6>,
|
||||||
|
<&adma 7>, <&adma 7>,
|
||||||
|
<&adma 8>, <&adma 8>,
|
||||||
|
<&adma 9>, <&adma 9>,
|
||||||
|
<&adma 10>, <&adma 10>;
|
||||||
|
dma-names = "rx1", "tx1",
|
||||||
|
"rx2", "tx2",
|
||||||
|
"rx3", "tx3",
|
||||||
|
"rx4", "tx4",
|
||||||
|
"rx5", "tx5",
|
||||||
|
"rx6", "tx6",
|
||||||
|
"rx7", "tx7",
|
||||||
|
"rx8", "tx8",
|
||||||
|
"rx9", "tx9",
|
||||||
|
"rx10", "tx10";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s1: i2s@702d1000 {
|
||||||
|
compatible = "nvidia,tegra210-i2s";
|
||||||
|
reg = <0x702d1000 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_I2S0>,
|
||||||
|
<&tegra_car TEGRA210_CLK_I2S0_SYNC>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s2: i2s@702d1100 {
|
||||||
|
compatible = "nvidia,tegra210-i2s";
|
||||||
|
reg = <0x702d1100 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_I2S1>,
|
||||||
|
<&tegra_car TEGRA210_CLK_I2S1_SYNC>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s3: i2s@702d1200 {
|
||||||
|
compatible = "nvidia,tegra210-i2s";
|
||||||
|
reg = <0x702d1200 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_I2S2>,
|
||||||
|
<&tegra_car TEGRA210_CLK_I2S2_SYNC>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S3";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s4: i2s@702d1300 {
|
||||||
|
compatible = "nvidia,tegra210-i2s";
|
||||||
|
reg = <0x702d1300 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_I2S3>,
|
||||||
|
<&tegra_car TEGRA210_CLK_I2S3_SYNC>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S4";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_i2s5: i2s@702d1400 {
|
||||||
|
compatible = "nvidia,tegra210-i2s";
|
||||||
|
reg = <0x702d1400 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_I2S4>,
|
||||||
|
<&tegra_car TEGRA210_CLK_I2S4_SYNC>;
|
||||||
|
clock-names = "i2s", "sync_input";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <1536000>;
|
||||||
|
sound-name-prefix = "I2S5";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic1: dmic@702d4000 {
|
||||||
|
compatible = "nvidia,tegra210-dmic";
|
||||||
|
reg = <0x702d4000 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC1";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic2: dmic@702d4100 {
|
||||||
|
compatible = "nvidia,tegra210-dmic";
|
||||||
|
reg = <0x702d4100 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC2";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
tegra_dmic3: dmic@702d4200 {
|
||||||
|
compatible = "nvidia,tegra210-dmic";
|
||||||
|
reg = <0x702d4200 0x100>;
|
||||||
|
clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
|
||||||
|
clock-names = "dmic";
|
||||||
|
assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
|
||||||
|
assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
|
||||||
|
assigned-clock-rates = <3072000>;
|
||||||
|
sound-name-prefix = "DMIC3";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
spi@70410000 {
|
spi@70410000 {
|
||||||
|
|
|
||||||
40
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts
Normal file
40
arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts
Normal file
|
|
@ -0,0 +1,40 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
#include "tegra234.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "NVIDIA Tegra234 VDK";
|
||||||
|
compatible = "nvidia,tegra234-vdk", "nvidia,tegra234";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
sdhci3 = "/cbb@0/sdhci@3460000";
|
||||||
|
serial0 = &uarta;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000";
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
cbb@0 {
|
||||||
|
serial@3100000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
sdhci@3460000 {
|
||||||
|
status = "okay";
|
||||||
|
bus-width = <8>;
|
||||||
|
non-removable;
|
||||||
|
only-1-8-v;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@c2a0000 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
pmc@c360000 {
|
||||||
|
nvidia,invert-interrupt;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
189
arch/arm64/boot/dts/nvidia/tegra234.dtsi
Normal file
189
arch/arm64/boot/dts/nvidia/tegra234.dtsi
Normal file
|
|
@ -0,0 +1,189 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0
|
||||||
|
|
||||||
|
#include <dt-bindings/clock/tegra234-clock.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/mailbox/tegra186-hsp.h>
|
||||||
|
#include <dt-bindings/reset/tegra234-reset.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "nvidia,tegra234";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
bus@0 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
ranges = <0x0 0x0 0x0 0x40000000>;
|
||||||
|
|
||||||
|
misc@100000 {
|
||||||
|
compatible = "nvidia,tegra234-misc";
|
||||||
|
reg = <0x00100000 0xf000>,
|
||||||
|
<0x0010f000 0x1000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
uarta: serial@3100000 {
|
||||||
|
compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
|
||||||
|
reg = <0x03100000 0x10000>;
|
||||||
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&bpmp TEGRA234_CLK_UARTA>;
|
||||||
|
clock-names = "serial";
|
||||||
|
resets = <&bpmp TEGRA234_RESET_UARTA>;
|
||||||
|
reset-names = "serial";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc@3460000 {
|
||||||
|
compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
|
||||||
|
reg = <0x03460000 0x20000>;
|
||||||
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&bpmp TEGRA234_CLK_SDMMC4>;
|
||||||
|
clock-names = "sdhci";
|
||||||
|
resets = <&bpmp TEGRA234_RESET_SDMMC4>;
|
||||||
|
reset-names = "sdhci";
|
||||||
|
dma-coherent;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
fuse@3810000 {
|
||||||
|
compatible = "nvidia,tegra234-efuse";
|
||||||
|
reg = <0x03810000 0x10000>;
|
||||||
|
clocks = <&bpmp TEGRA234_CLK_FUSE>;
|
||||||
|
clock-names = "fuse";
|
||||||
|
};
|
||||||
|
|
||||||
|
hsp_top0: hsp@3c00000 {
|
||||||
|
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
|
||||||
|
reg = <0x03c00000 0xa0000>;
|
||||||
|
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "doorbell", "shared0", "shared1", "shared2",
|
||||||
|
"shared3", "shared4", "shared5", "shared6",
|
||||||
|
"shared7";
|
||||||
|
#mbox-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
hsp_aon: hsp@c150000 {
|
||||||
|
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
|
||||||
|
reg = <0x0c150000 0x90000>;
|
||||||
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
/*
|
||||||
|
* Shared interrupt 0 is routed only to AON/SPE, so
|
||||||
|
* we only have 4 shared interrupts for the CCPLEX.
|
||||||
|
*/
|
||||||
|
interrupt-names = "shared1", "shared2", "shared3", "shared4";
|
||||||
|
#mbox-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rtc@c2a0000 {
|
||||||
|
compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
|
||||||
|
reg = <0x0c2a0000 0x10000>;
|
||||||
|
interrupt-parent = <&pmc>;
|
||||||
|
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
pmc: pmc@c360000 {
|
||||||
|
compatible = "nvidia,tegra234-pmc";
|
||||||
|
reg = <0x0c360000 0x10000>,
|
||||||
|
<0x0c370000 0x10000>,
|
||||||
|
<0x0c380000 0x10000>,
|
||||||
|
<0x0c390000 0x10000>,
|
||||||
|
<0x0c3a0000 0x10000>;
|
||||||
|
reg-names = "pmc", "wake", "aotag", "scratch", "misc";
|
||||||
|
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
};
|
||||||
|
|
||||||
|
gic: interrupt-controller@f400000 {
|
||||||
|
compatible = "arm,gic-v3";
|
||||||
|
reg = <0x0f400000 0x010000>, /* GICD */
|
||||||
|
<0x0f440000 0x200000>; /* GICR */
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||||
|
|
||||||
|
#redistributor-regions = <1>;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
interrupt-controller;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
sysram@40000000 {
|
||||||
|
compatible = "nvidia,tegra234-sysram", "mmio-sram";
|
||||||
|
reg = <0x0 0x40000000 0x0 0x50000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x0 0x0 0x40000000 0x50000>;
|
||||||
|
|
||||||
|
cpu_bpmp_tx: shmem@4e000 {
|
||||||
|
reg = <0x4e000 0x1000>;
|
||||||
|
label = "cpu-bpmp-tx";
|
||||||
|
pool;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_bpmp_rx: shmem@4f000 {
|
||||||
|
reg = <0x4f000 0x1000>;
|
||||||
|
label = "cpu-bpmp-rx";
|
||||||
|
pool;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
bpmp: bpmp {
|
||||||
|
compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
|
||||||
|
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
|
||||||
|
TEGRA_HSP_DB_MASTER_BPMP>;
|
||||||
|
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
#power-domain-cells = <1>;
|
||||||
|
|
||||||
|
bpmp_i2c: i2c {
|
||||||
|
compatible = "nvidia,tegra186-bpmp-i2c";
|
||||||
|
nvidia,bpmp-bus-id = <5>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
reg = <0x000>;
|
||||||
|
|
||||||
|
enable-method = "psci";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
psci {
|
||||||
|
compatible = "arm,psci-1.0";
|
||||||
|
status = "okay";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||||
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
always-on;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -119,6 +119,16 @@ config ARCH_TEGRA_194_SOC
|
||||||
help
|
help
|
||||||
Enable support for the NVIDIA Tegra194 SoC.
|
Enable support for the NVIDIA Tegra194 SoC.
|
||||||
|
|
||||||
|
config ARCH_TEGRA_234_SOC
|
||||||
|
bool "NVIDIA Tegra234 SoC"
|
||||||
|
select MAILBOX
|
||||||
|
select TEGRA_BPMP
|
||||||
|
select TEGRA_HSP_MBOX
|
||||||
|
select TEGRA_IVC
|
||||||
|
select SOC_TEGRA_PMC
|
||||||
|
help
|
||||||
|
Enable support for the NVIDIA Tegra234 SoC.
|
||||||
|
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
|
|
||||||
14
include/dt-bindings/clock/tegra234-clock.h
Normal file
14
include/dt-bindings/clock/tegra234-clock.h
Normal file
|
|
@ -0,0 +1,14 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
|
||||||
|
|
||||||
|
#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
|
||||||
|
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
|
||||||
|
|
||||||
|
/** @brief output of gate CLK_ENB_FUSE */
|
||||||
|
#define TEGRA234_CLK_FUSE 40
|
||||||
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
|
||||||
|
#define TEGRA234_CLK_SDMMC4 123
|
||||||
|
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
|
||||||
|
#define TEGRA234_CLK_UARTA 155
|
||||||
|
|
||||||
|
#endif
|
||||||
10
include/dt-bindings/reset/tegra234-reset.h
Normal file
10
include/dt-bindings/reset/tegra234-reset.h
Normal file
|
|
@ -0,0 +1,10 @@
|
||||||
|
/* SPDX-License-Identifier: GPL-2.0 */
|
||||||
|
/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */
|
||||||
|
|
||||||
|
#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H
|
||||||
|
#define DT_BINDINGS_RESET_TEGRA234_RESET_H
|
||||||
|
|
||||||
|
#define TEGRA234_RESET_SDMMC4 85
|
||||||
|
#define TEGRA234_RESET_UARTA 100
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Reference in New Issue
Block a user