forked from luck/tmp_suning_uos_patched
4716e488ab
Commit350779a29f("powerpc: Handle most loads and stores in instruction emulation code", 2017-08-30) changed the register usage in get_vr and put_vr with the aim of leaving the register number in r3 untouched on return. Unfortunately, r6 was not a good choice, as the callers as of350779a29fstore a MSR value in r6. Then, in commitc22435a5f3("powerpc: Emulate FP/vector/VSX loads/stores correctly when regs not live", 2017-08-30), the saving and restoring of the MSR got moved into get_vr and put_vr. Either way, the effect is that we put a value in MSR that only has the 0x3f8 bits non-zero, meaning that we are switching to 32-bit mode. That leads to a crash like this: Unable to handle kernel paging request for instruction fetch Faulting instruction address: 0x0007bea0 Oops: Kernel access of bad area, sig: 11 [#12] LE SMP NR_CPUS=2048 NUMA PowerNV Modules linked in: vmx_crypto binfmt_misc ip_tables x_tables autofs4 crc32c_vpmsum CPU: 6 PID: 32659 Comm: trashy_testcase Tainted: G D 4.13.0-rc2-00313-gf3026f57e6ed-dirty #23 task: c000000f1bb9e780 task.stack: c000000f1ba98000 NIP: 000000000007bea0 LR: c00000000007b054 CTR: c00000000007be70 REGS: c000000f1ba9b960 TRAP: 0400 Tainted: G D (4.13.0-rc2-00313-gf3026f57e6ed-dirty) MSR: 10000000400010a1 <HV,ME,IR,LE> CR: 48000228 XER: 00000000 CFAR: c00000000007be74 SOFTE: 1 GPR00: c00000000007b054 c000000f1ba9bbe0 c000000000e6e000 000000000000001d GPR04: c000000f1ba9bc00 c00000000007be70 00000000000000e8 9000000002009033 GPR08: 0000000002000000 100000000282f033 000000000b0a0900 0000000000001009 GPR12: 0000000000000000 c00000000fd42100 0706050303020100 a5a5a5a5a5a5a5a5 GPR16: 2e2e2e2e2e2de70c 2e2e2e2e2e2e2e2d 0000000000ff00ff 0606040202020000 GPR20: 000000000000005b ffffffffffffffff 0000000003020100 0000000000000000 GPR24: c000000f1ab90020 c000000f1ba9bc00 0000000000000001 0000000000000001 GPR28: c000000f1ba9bc90 c000000f1ba9bea0 000000000b0a0908 0000000000000001 NIP [000000000007bea0] 0x7bea0 LR [c00000000007b054] emulate_loadstore+0x1044/0x1280 Call Trace: [c000000f1ba9bbe0] [c000000000076b80] analyse_instr+0x60/0x34f0 (unreliable) [c000000f1ba9bc70] [c00000000007b7ec] emulate_step+0x23c/0x544 [c000000f1ba9bce0] [c000000000053424] arch_uprobe_skip_sstep+0x24/0x40 [c000000f1ba9bd00] [c00000000024b2f8] uprobe_notify_resume+0x598/0xba0 [c000000f1ba9be00] [c00000000001c284] do_notify_resume+0xd4/0xf0 [c000000f1ba9be30] [c00000000000bd44] ret_from_except_lite+0x70/0x74 Instruction dump: XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ---[ end trace a7ae7a7f3e0256b5 ]--- To fix this, we just revert to using r3 as before, since the callers don't rely on r3 being left unmodified. Fortunately, this can't be triggered by a misaligned load or store, because vector loads and stores truncate misaligned addresses rather than taking an alignment interrupt. It can be triggered using uprobes. Fixes:350779a29f("powerpc: Handle most loads and stores in instruction emulation code") Reported-by: Anton Blanchard <anton@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Tested-by: Anton Blanchard <anton@samba.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
245 lines
3.9 KiB
ArmAsm
245 lines
3.9 KiB
ArmAsm
/*
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* Floating-point, VMX/Altivec and VSX loads and stores
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* for use in instruction emulation.
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*
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* Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/reg.h>
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#include <asm/asm-offsets.h>
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#include <linux/errno.h>
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#ifdef CONFIG_PPC_FPU
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#define STKFRM (PPC_MIN_STKFRM + 16)
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/* Get the contents of frN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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stfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of *p into frN; N is in r3 and p is in r4. */
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_GLOBAL(put_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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lfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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#ifdef CONFIG_ALTIVEC
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/* Get the contents of vrN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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stvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of *p into vrN; N is in r3 and p is in r4. */
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_GLOBAL(put_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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lvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_VSX
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/* Get the contents of vsN into vs0; N is in r3. */
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_GLOBAL(get_vsr)
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mflr r0
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rlwinm r3,r3,3,0x1f8
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bcl 20,31,1f
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blr /* vs0 is already in vs0 */
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nop
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reg = 1
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.rept 63
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XXLOR(0,reg,reg)
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blr
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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/* Put the contents of vs0 into vsN; N is in r3. */
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_GLOBAL(put_vsr)
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mflr r0
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rlwinm r3,r3,3,0x1f8
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bcl 20,31,1f
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blr /* v0 is already in v0 */
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nop
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reg = 1
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.rept 63
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XXLOR(reg,0,0)
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blr
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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/* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */
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_GLOBAL(load_vsrn)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VSX@h
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cmpwi cr7,r3,0
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li r8,STKFRM-16
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MTMSRD(r7)
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isync
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beq cr7,1f
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STXVD2X(0,R1,R8)
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1: LXVD2X(0,R0,R4)
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#ifdef __LITTLE_ENDIAN__
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XXSWAPD(0,0)
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#endif
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beq cr7,4f
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bl put_vsr
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LXVD2X(0,R1,R8)
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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addi r1,r1,STKFRM
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blr
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/* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */
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_GLOBAL(store_vsrn)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VSX@h
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li r8,STKFRM-16
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MTMSRD(r7)
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isync
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STXVD2X(0,R1,R8)
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bl get_vsr
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#ifdef __LITTLE_ENDIAN__
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XXSWAPD(0,0)
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#endif
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STXVD2X(0,R0,R4)
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LXVD2X(0,R1,R8)
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PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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#endif /* CONFIG_VSX */
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/* Convert single-precision to double, without disturbing FPRs. */
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/* conv_sp_to_dp(float *sp, double *dp) */
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_GLOBAL(conv_sp_to_dp)
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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stfd fr0, -16(r1)
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lfs fr0, 0(r3)
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stfd fr0, 0(r4)
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lfd fr0, -16(r1)
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MTMSRD(r6)
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isync
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blr
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/* Convert single-precision to double, without disturbing FPRs. */
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/* conv_sp_to_dp(double *dp, float *sp) */
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_GLOBAL(conv_dp_to_sp)
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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stfd fr0, -16(r1)
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lfd fr0, 0(r3)
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stfs fr0, 0(r4)
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lfd fr0, -16(r1)
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MTMSRD(r6)
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isync
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blr
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#endif /* CONFIG_PPC_FPU */
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