forked from luck/tmp_suning_uos_patched
Merge branches 'clk-phase-errors', 'clk-amlogic', 'clk-renesas' and 'clk-allwinner' into clk-next
- Don't show clk phase when it is invalid * clk-phase-errors: clk: rockchip: fix mmc get phase clk: Fix phase init check clk: Bail out when calculating phase fails during clk registration clk: Move rate and accuracy recalc to mostly consumer APIs clk: Use 'parent' to shorten lines in __clk_core_init() clk: Don't cache errors from clk_ops::get_phase() * clk-amlogic: clk: meson: meson8b: set audio output clock hierarchy clk: meson: g12a: add support for the SPICC SCLK Source clocks dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs clk: meson: gxbb: set audio output clock hierarchy clk: meson: gxbb: add the gxl internal dac gate dt-bindings: clk: meson: add the gxl internal dac gate * clk-renesas: dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema clk: renesas: rcar-usb2-clock-sel: Add reset_control clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties clk: renesas: Remove use of ARCH_R8A7795 clk: renesas: r8a77965: Add RPC clocks clk: renesas: r8a7796: Add RPC clocks clk: renesas: r8a7795: Add RPC clocks clk: renesas: rcar-gen3: Add CCREE clocks * clk-allwinner: clk: sunxi-ng: sun8i-de2: Sort structures clk: sunxi-ng: sun8i-de2: Add R40 specific quirks clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64 clk: sunxi-ng: sun8i-de2: Split out H5 definitions clk: sunxi-ng: a64: Export MBUS clock
This commit is contained in:
Stephen Boyd
commit
2d11e9a1fd
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|
@ -1,100 +0,0 @@
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|||
* Renesas Clock Pulse Generator / Module Standby and Software Reset
|
||||
|
||||
On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
|
||||
and MSSR (Module Standby and Software Reset) blocks are intimately connected,
|
||||
and share the same register block.
|
||||
|
||||
They provide the following functionalities:
|
||||
- The CPG block generates various core clocks,
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||||
- The MSSR block provides two functions:
|
||||
1. Module Standby, providing a Clock Domain to control the clock supply
|
||||
to individual SoC devices,
|
||||
2. Reset Control, to perform a software reset of individual SoC devices.
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||||
|
||||
Required Properties:
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||||
- compatible: Must be one of:
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||||
- "renesas,r7s9210-cpg-mssr" for the r7s9210 SoC (RZ/A2)
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- "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
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||||
- "renesas,r8a7744-cpg-mssr" for the r8a7744 SoC (RZ/G1N)
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- "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)
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||||
- "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)
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- "renesas,r8a774a1-cpg-mssr" for the r8a774a1 SoC (RZ/G2M)
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||||
- "renesas,r8a774b1-cpg-mssr" for the r8a774b1 SoC (RZ/G2N)
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- "renesas,r8a774c0-cpg-mssr" for the r8a774c0 SoC (RZ/G2E)
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||||
- "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)
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||||
- "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)
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||||
- "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
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||||
- "renesas,r8a7793-cpg-mssr" for the r8a7793 SoC (R-Car M2-N)
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- "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
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- "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
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- "renesas,r8a7796-cpg-mssr" for the r8a77960 SoC (R-Car M3-W)
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- "renesas,r8a77961-cpg-mssr" for the r8a77961 SoC (R-Car M3-W+)
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- "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)
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- "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
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||||
- "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)
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- "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)
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- "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
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- reg: Base address and length of the memory resource used by the CPG/MSSR
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block
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- clocks: References to external parent clocks, one entry for each entry in
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clock-names
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- clock-names: List of external parent clock names. Valid names are:
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- "extal" (r7s9210, r8a7743, r8a7744, r8a7745, r8a77470, r8a774a1,
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r8a774b1, r8a774c0, r8a7790, r8a7791, r8a7792, r8a7793,
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||||
r8a7794, r8a7795, r8a77960, r8a77961, r8a77965, r8a77970,
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r8a77980, r8a77990, r8a77995)
|
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- "extalr" (r8a774a1, r8a774b1, r8a7795, r8a77960, r8a77961, r8a77965,
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r8a77970, r8a77980)
|
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- "usb_extal" (r8a7743, r8a7744, r8a7745, r8a77470, r8a7790, r8a7791,
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r8a7793, r8a7794)
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||||
|
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- #clock-cells: Must be 2
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/*-cpg-mssr.h>.
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the datasheet.
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||||
|
||||
- #power-domain-cells: Must be 0
|
||||
- SoC devices that are part of the CPG/MSSR Clock Domain and can be
|
||||
power-managed through Module Standby should refer to the CPG device
|
||||
node in their "power-domains" property, as documented by the generic PM
|
||||
Domain bindings in
|
||||
Documentation/devicetree/bindings/power/power-domain.yaml.
|
||||
|
||||
- #reset-cells: Must be 1
|
||||
- The single reset specifier cell must be the module number, as defined
|
||||
in the datasheet.
|
||||
|
||||
|
||||
Examples
|
||||
--------
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|
||||
- CPG device node:
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|
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7795-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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||||
};
|
||||
|
||||
|
||||
- CPG/MSSR Clock Domain member device node:
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|
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scif2: serial@e6e88000 {
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compatible = "renesas,scif-r8a7795", "renesas,scif";
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reg = <0 0xe6e88000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 310>;
|
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clock-names = "fck";
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dmas = <&dmac1 0x13>, <&dmac1 0x12>;
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dma-names = "tx", "rx";
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power-domains = <&cpg>;
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resets = <&cpg 310>;
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||||
};
|
||||
119
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
Normal file
119
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Renesas Clock Pulse Generator / Module Standby and Software Reset
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description: |
|
||||
On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
|
||||
and MSSR (Module Standby and Software Reset) blocks are intimately connected,
|
||||
and share the same register block.
|
||||
|
||||
They provide the following functionalities:
|
||||
- The CPG block generates various core clocks,
|
||||
- The MSSR block provides two functions:
|
||||
1. Module Standby, providing a Clock Domain to control the clock supply
|
||||
to individual SoC devices,
|
||||
2. Reset Control, to perform a software reset of individual SoC devices.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,r7s9210-cpg-mssr # RZ/A2
|
||||
- renesas,r8a7743-cpg-mssr # RZ/G1M
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||||
- renesas,r8a7744-cpg-mssr # RZ/G1N
|
||||
- renesas,r8a7745-cpg-mssr # RZ/G1E
|
||||
- renesas,r8a77470-cpg-mssr # RZ/G1C
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||||
- renesas,r8a774a1-cpg-mssr # RZ/G2M
|
||||
- renesas,r8a774b1-cpg-mssr # RZ/G2N
|
||||
- renesas,r8a774c0-cpg-mssr # RZ/G2E
|
||||
- renesas,r8a7790-cpg-mssr # R-Car H2
|
||||
- renesas,r8a7791-cpg-mssr # R-Car M2-W
|
||||
- renesas,r8a7792-cpg-mssr # R-Car V2H
|
||||
- renesas,r8a7793-cpg-mssr # R-Car M2-N
|
||||
- renesas,r8a7794-cpg-mssr # R-Car E2
|
||||
- renesas,r8a7795-cpg-mssr # R-Car H3
|
||||
- renesas,r8a7796-cpg-mssr # R-Car M3-W
|
||||
- renesas,r8a77961-cpg-mssr # R-Car M3-W+
|
||||
- renesas,r8a77965-cpg-mssr # R-Car M3-N
|
||||
- renesas,r8a77970-cpg-mssr # R-Car V3M
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||||
- renesas,r8a77980-cpg-mssr # R-Car V3H
|
||||
- renesas,r8a77990-cpg-mssr # R-Car E3
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- renesas,r8a77995-cpg-mssr # R-Car D3
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|
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reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
enum:
|
||||
- extal # All
|
||||
- extalr # Most R-Car Gen3 and RZ/G2
|
||||
- usb_extal # Most R-Car Gen2 and RZ/G1
|
||||
|
||||
'#clock-cells':
|
||||
description: |
|
||||
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
|
||||
and a core clock reference, as defined in
|
||||
<dt-bindings/clock/*-cpg-mssr.h>
|
||||
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
|
||||
a module number, as defined in the datasheet.
|
||||
const: 2
|
||||
|
||||
'#power-domain-cells':
|
||||
description:
|
||||
SoC devices that are part of the CPG/MSSR Clock Domain and can be
|
||||
power-managed through Module Standby should refer to the CPG device node
|
||||
in their "power-domains" property, as documented by the generic PM Domain
|
||||
bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
|
||||
const: 0
|
||||
|
||||
'#reset-cells':
|
||||
description:
|
||||
The single reset specifier cell must be the module number, as defined in
|
||||
the datasheet.
|
||||
const: 1
|
||||
|
||||
if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
enum:
|
||||
- renesas,r7s9210-cpg-mssr
|
||||
then:
|
||||
required:
|
||||
- '#reset-cells'
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7795-cpg-mssr";
|
||||
reg = <0xe6150000 0x1000>;
|
||||
clocks = <&extal_clk>, <&extalr_clk>;
|
||||
clock-names = "extal", "extalr";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -38,10 +38,17 @@ Required properties:
|
|||
- reg: offset and length of the USB 2.0 clock selector register block.
|
||||
- clocks: A list of phandles and specifier pairs.
|
||||
- clock-names: Name of the clocks.
|
||||
- The functional clock must be "ehci_ohci"
|
||||
- The functional clock of USB 2.0 host side must be "ehci_ohci"
|
||||
- The functional clock of HS-USB side must be "hs-usb-if"
|
||||
- The USB_EXTAL clock pin must be "usb_extal"
|
||||
- The USB_XTAL clock pin must be "usb_xtal"
|
||||
- #clock-cells: Must be 0
|
||||
- power-domains: A phandle and symbolic PM domain specifier.
|
||||
See power/renesas,rcar-sysc.yaml.
|
||||
- resets: A list of phandles and specifier pairs.
|
||||
- reset-names: Name of the resets.
|
||||
- The reset of USB 2.0 host side must be "ehci_ohci"
|
||||
- The reset of HS-USB side must be "hs-usb-if"
|
||||
|
||||
Example (R-Car H3):
|
||||
|
||||
|
|
@ -49,7 +56,11 @@ Example (R-Car H3):
|
|||
compatible = "renesas,r8a7795-rcar-usb2-clock-sel",
|
||||
"renesas,rcar-gen3-usb2-clock-sel";
|
||||
reg = <0 0xe6590630 0 0x02>;
|
||||
clocks = <&cpg CPG_MOD 703>, <&usb_extal>, <&usb_xtal>;
|
||||
clock-names = "ehci_ohci", "usb_extal", "usb_xtal";
|
||||
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
|
||||
<&usb_extal>, <&usb_xtal>;
|
||||
clock-names = "ehci_ohci", "hs-usb-if", "usb_extal", "usb_xtal";
|
||||
#clock-cells = <0>;
|
||||
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 703>, <&cpg 704>;
|
||||
reset-names = "ehci_ohci", "hs-usb-if";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -488,7 +488,7 @@ unsigned long clk_hw_get_rate(const struct clk_hw *hw)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(clk_hw_get_rate);
|
||||
|
||||
static unsigned long __clk_get_accuracy(struct clk_core *core)
|
||||
static unsigned long clk_core_get_accuracy_no_lock(struct clk_core *core)
|
||||
{
|
||||
if (!core)
|
||||
return 0;
|
||||
|
|
@ -1517,18 +1517,12 @@ static void __clk_recalc_accuracies(struct clk_core *core)
|
|||
__clk_recalc_accuracies(child);
|
||||
}
|
||||
|
||||
static long clk_core_get_accuracy(struct clk_core *core)
|
||||
static long clk_core_get_accuracy_recalc(struct clk_core *core)
|
||||
{
|
||||
unsigned long accuracy;
|
||||
|
||||
clk_prepare_lock();
|
||||
if (core && (core->flags & CLK_GET_ACCURACY_NOCACHE))
|
||||
__clk_recalc_accuracies(core);
|
||||
|
||||
accuracy = __clk_get_accuracy(core);
|
||||
clk_prepare_unlock();
|
||||
|
||||
return accuracy;
|
||||
return clk_core_get_accuracy_no_lock(core);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1542,10 +1536,16 @@ static long clk_core_get_accuracy(struct clk_core *core)
|
|||
*/
|
||||
long clk_get_accuracy(struct clk *clk)
|
||||
{
|
||||
long accuracy;
|
||||
|
||||
if (!clk)
|
||||
return 0;
|
||||
|
||||
return clk_core_get_accuracy(clk->core);
|
||||
clk_prepare_lock();
|
||||
accuracy = clk_core_get_accuracy_recalc(clk->core);
|
||||
clk_prepare_unlock();
|
||||
|
||||
return accuracy;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_accuracy);
|
||||
|
||||
|
|
@ -1599,19 +1599,12 @@ static void __clk_recalc_rates(struct clk_core *core, unsigned long msg)
|
|||
__clk_recalc_rates(child, msg);
|
||||
}
|
||||
|
||||
static unsigned long clk_core_get_rate(struct clk_core *core)
|
||||
static unsigned long clk_core_get_rate_recalc(struct clk_core *core)
|
||||
{
|
||||
unsigned long rate;
|
||||
|
||||
clk_prepare_lock();
|
||||
|
||||
if (core && (core->flags & CLK_GET_RATE_NOCACHE))
|
||||
__clk_recalc_rates(core, 0);
|
||||
|
||||
rate = clk_core_get_rate_nolock(core);
|
||||
clk_prepare_unlock();
|
||||
|
||||
return rate;
|
||||
return clk_core_get_rate_nolock(core);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1624,10 +1617,16 @@ static unsigned long clk_core_get_rate(struct clk_core *core)
|
|||
*/
|
||||
unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
unsigned long rate;
|
||||
|
||||
if (!clk)
|
||||
return 0;
|
||||
|
||||
return clk_core_get_rate(clk->core);
|
||||
clk_prepare_lock();
|
||||
rate = clk_core_get_rate_recalc(clk->core);
|
||||
clk_prepare_unlock();
|
||||
|
||||
return rate;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_rate);
|
||||
|
||||
|
|
@ -2660,12 +2659,14 @@ static int clk_core_get_phase(struct clk_core *core)
|
|||
{
|
||||
int ret;
|
||||
|
||||
clk_prepare_lock();
|
||||
lockdep_assert_held(&prepare_lock);
|
||||
if (!core->ops->get_phase)
|
||||
return 0;
|
||||
|
||||
/* Always try to update cached phase if possible */
|
||||
if (core->ops->get_phase)
|
||||
core->phase = core->ops->get_phase(core->hw);
|
||||
ret = core->phase;
|
||||
clk_prepare_unlock();
|
||||
ret = core->ops->get_phase(core->hw);
|
||||
if (ret >= 0)
|
||||
core->phase = ret;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -2679,10 +2680,16 @@ static int clk_core_get_phase(struct clk_core *core)
|
|||
*/
|
||||
int clk_get_phase(struct clk *clk)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!clk)
|
||||
return 0;
|
||||
|
||||
return clk_core_get_phase(clk->core);
|
||||
clk_prepare_lock();
|
||||
ret = clk_core_get_phase(clk->core);
|
||||
clk_prepare_unlock();
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_phase);
|
||||
|
||||
|
|
@ -2896,13 +2903,22 @@ static struct hlist_head *orphan_list[] = {
|
|||
static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
|
||||
int level)
|
||||
{
|
||||
seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
|
||||
int phase;
|
||||
|
||||
seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu ",
|
||||
level * 3 + 1, "",
|
||||
30 - level * 3, c->name,
|
||||
c->enable_count, c->prepare_count, c->protect_count,
|
||||
clk_core_get_rate(c), clk_core_get_accuracy(c),
|
||||
clk_core_get_phase(c),
|
||||
clk_core_get_scaled_duty_cycle(c, 100000));
|
||||
clk_core_get_rate_recalc(c),
|
||||
clk_core_get_accuracy_recalc(c));
|
||||
|
||||
phase = clk_core_get_phase(c);
|
||||
if (phase >= 0)
|
||||
seq_printf(s, "%5d", phase);
|
||||
else
|
||||
seq_puts(s, "-----");
|
||||
|
||||
seq_printf(s, " %6d\n", clk_core_get_scaled_duty_cycle(c, 100000));
|
||||
}
|
||||
|
||||
static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
|
||||
|
|
@ -2939,6 +2955,7 @@ DEFINE_SHOW_ATTRIBUTE(clk_summary);
|
|||
|
||||
static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
|
||||
{
|
||||
int phase;
|
||||
unsigned long min_rate, max_rate;
|
||||
|
||||
clk_core_get_boundaries(c, &min_rate, &max_rate);
|
||||
|
|
@ -2948,11 +2965,13 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
|
|||
seq_printf(s, "\"enable_count\": %d,", c->enable_count);
|
||||
seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
|
||||
seq_printf(s, "\"protect_count\": %d,", c->protect_count);
|
||||
seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
|
||||
seq_printf(s, "\"rate\": %lu,", clk_core_get_rate_recalc(c));
|
||||
seq_printf(s, "\"min_rate\": %lu,", min_rate);
|
||||
seq_printf(s, "\"max_rate\": %lu,", max_rate);
|
||||
seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
|
||||
seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
|
||||
seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy_recalc(c));
|
||||
phase = clk_core_get_phase(c);
|
||||
if (phase >= 0)
|
||||
seq_printf(s, "\"phase\": %d,", phase);
|
||||
seq_printf(s, "\"duty_cycle\": %u",
|
||||
clk_core_get_scaled_duty_cycle(c, 100000));
|
||||
}
|
||||
|
|
@ -3323,7 +3342,9 @@ static void clk_core_reparent_orphans_nolock(void)
|
|||
static int __clk_core_init(struct clk_core *core)
|
||||
{
|
||||
int ret;
|
||||
struct clk_core *parent;
|
||||
unsigned long rate;
|
||||
int phase;
|
||||
|
||||
if (!core)
|
||||
return -EINVAL;
|
||||
|
|
@ -3394,7 +3415,7 @@ static int __clk_core_init(struct clk_core *core)
|
|||
goto out;
|
||||
}
|
||||
|
||||
core->parent = __clk_init_parent(core);
|
||||
parent = core->parent = __clk_init_parent(core);
|
||||
|
||||
/*
|
||||
* Populate core->parent if parent has already been clk_core_init'd. If
|
||||
|
|
@ -3406,10 +3427,9 @@ static int __clk_core_init(struct clk_core *core)
|
|||
* clocks and re-parent any that are children of the clock currently
|
||||
* being clk_init'd.
|
||||
*/
|
||||
if (core->parent) {
|
||||
hlist_add_head(&core->child_node,
|
||||
&core->parent->children);
|
||||
core->orphan = core->parent->orphan;
|
||||
if (parent) {
|
||||
hlist_add_head(&core->child_node, &parent->children);
|
||||
core->orphan = parent->orphan;
|
||||
} else if (!core->num_parents) {
|
||||
hlist_add_head(&core->child_node, &clk_root_list);
|
||||
core->orphan = false;
|
||||
|
|
@ -3427,21 +3447,24 @@ static int __clk_core_init(struct clk_core *core)
|
|||
*/
|
||||
if (core->ops->recalc_accuracy)
|
||||
core->accuracy = core->ops->recalc_accuracy(core->hw,
|
||||
__clk_get_accuracy(core->parent));
|
||||
else if (core->parent)
|
||||
core->accuracy = core->parent->accuracy;
|
||||
clk_core_get_accuracy_no_lock(parent));
|
||||
else if (parent)
|
||||
core->accuracy = parent->accuracy;
|
||||
else
|
||||
core->accuracy = 0;
|
||||
|
||||
/*
|
||||
* Set clk's phase.
|
||||
* Set clk's phase by clk_core_get_phase() caching the phase.
|
||||
* Since a phase is by definition relative to its parent, just
|
||||
* query the current clock phase, or just assume it's in phase.
|
||||
*/
|
||||
if (core->ops->get_phase)
|
||||
core->phase = core->ops->get_phase(core->hw);
|
||||
else
|
||||
core->phase = 0;
|
||||
phase = clk_core_get_phase(core);
|
||||
if (phase < 0) {
|
||||
ret = phase;
|
||||
pr_warn("%s: Failed to get phase for clk '%s'\n", __func__,
|
||||
core->name);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set clk's duty cycle.
|
||||
|
|
@ -3456,9 +3479,9 @@ static int __clk_core_init(struct clk_core *core)
|
|||
*/
|
||||
if (core->ops->recalc_rate)
|
||||
rate = core->ops->recalc_rate(core->hw,
|
||||
clk_core_get_rate_nolock(core->parent));
|
||||
else if (core->parent)
|
||||
rate = core->parent->rate;
|
||||
clk_core_get_rate_nolock(parent));
|
||||
else if (parent)
|
||||
rate = parent->rate;
|
||||
else
|
||||
rate = 0;
|
||||
core->rate = core->req_rate = rate;
|
||||
|
|
|
|||
|
|
@ -3862,6 +3862,111 @@ static struct clk_regmap g12a_ts = {
|
|||
},
|
||||
};
|
||||
|
||||
/* SPICC SCLK source clock */
|
||||
|
||||
static const struct clk_parent_data spicc_sclk_parent_data[] = {
|
||||
{ .fw_name = "xtal", },
|
||||
{ .hw = &g12a_clk81.hw },
|
||||
{ .hw = &g12a_fclk_div4.hw },
|
||||
{ .hw = &g12a_fclk_div3.hw },
|
||||
{ .hw = &g12a_fclk_div5.hw },
|
||||
{ .hw = &g12a_fclk_div7.hw },
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_spicc0_sclk_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SPICC_CLK_CNTL,
|
||||
.mask = 7,
|
||||
.shift = 7,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "spicc0_sclk_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_data = spicc_sclk_parent_data,
|
||||
.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_spicc0_sclk_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SPICC_CLK_CNTL,
|
||||
.shift = 0,
|
||||
.width = 6,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "spicc0_sclk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&g12a_spicc0_sclk_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_spicc0_sclk = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SPICC_CLK_CNTL,
|
||||
.bit_idx = 6,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "spicc0_sclk",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&g12a_spicc0_sclk_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_spicc1_sclk_sel = {
|
||||
.data = &(struct clk_regmap_mux_data){
|
||||
.offset = HHI_SPICC_CLK_CNTL,
|
||||
.mask = 7,
|
||||
.shift = 23,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "spicc1_sclk_sel",
|
||||
.ops = &clk_regmap_mux_ops,
|
||||
.parent_data = spicc_sclk_parent_data,
|
||||
.num_parents = ARRAY_SIZE(spicc_sclk_parent_data),
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_spicc1_sclk_div = {
|
||||
.data = &(struct clk_regmap_div_data){
|
||||
.offset = HHI_SPICC_CLK_CNTL,
|
||||
.shift = 16,
|
||||
.width = 6,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "spicc1_sclk_div",
|
||||
.ops = &clk_regmap_divider_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&g12a_spicc1_sclk_sel.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap g12a_spicc1_sclk = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
.offset = HHI_SPICC_CLK_CNTL,
|
||||
.bit_idx = 22,
|
||||
},
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "spicc1_sclk",
|
||||
.ops = &clk_regmap_gate_ops,
|
||||
.parent_hws = (const struct clk_hw *[]) {
|
||||
&g12a_spicc1_sclk_div.hw
|
||||
},
|
||||
.num_parents = 1,
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
},
|
||||
};
|
||||
|
||||
#define MESON_GATE(_name, _reg, _bit) \
|
||||
MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
|
||||
|
||||
|
|
@ -4159,6 +4264,12 @@ static struct clk_hw_onecell_data g12a_hw_onecell_data = {
|
|||
[CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
|
||||
[CLKID_TS_DIV] = &g12a_ts_div.hw,
|
||||
[CLKID_TS] = &g12a_ts.hw,
|
||||
[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
|
||||
[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
|
||||
[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
|
||||
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
|
||||
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
|
||||
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -4408,6 +4519,12 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
|
|||
[CLKID_CPUB_CLK_AXI] = &g12b_cpub_clk_axi.hw,
|
||||
[CLKID_CPUB_CLK_TRACE_SEL] = &g12b_cpub_clk_trace_sel.hw,
|
||||
[CLKID_CPUB_CLK_TRACE] = &g12b_cpub_clk_trace.hw,
|
||||
[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
|
||||
[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
|
||||
[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
|
||||
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
|
||||
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
|
||||
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -4642,6 +4759,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
|
|||
[CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
|
||||
[CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
|
||||
[CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
|
||||
[CLKID_SPICC0_SCLK_SEL] = &g12a_spicc0_sclk_sel.hw,
|
||||
[CLKID_SPICC0_SCLK_DIV] = &g12a_spicc0_sclk_div.hw,
|
||||
[CLKID_SPICC0_SCLK] = &g12a_spicc0_sclk.hw,
|
||||
[CLKID_SPICC1_SCLK_SEL] = &g12a_spicc1_sclk_sel.hw,
|
||||
[CLKID_SPICC1_SCLK_DIV] = &g12a_spicc1_sclk_div.hw,
|
||||
[CLKID_SPICC1_SCLK] = &g12a_spicc1_sclk.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -4877,6 +5000,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
|
|||
&sm1_cpu1_clk,
|
||||
&sm1_cpu2_clk,
|
||||
&sm1_cpu3_clk,
|
||||
&g12a_spicc0_sclk_sel,
|
||||
&g12a_spicc0_sclk_div,
|
||||
&g12a_spicc0_sclk,
|
||||
&g12a_spicc1_sclk_sel,
|
||||
&g12a_spicc1_sclk_div,
|
||||
&g12a_spicc1_sclk,
|
||||
};
|
||||
|
||||
static const struct reg_sequence g12a_init_regs[] = {
|
||||
|
|
|
|||
|
|
@ -255,8 +255,12 @@
|
|||
#define CLKID_DSU_CLK_DYN1 249
|
||||
#define CLKID_DSU_CLK_DYN 250
|
||||
#define CLKID_DSU_CLK_FINAL 251
|
||||
#define CLKID_SPICC0_SCLK_SEL 256
|
||||
#define CLKID_SPICC0_SCLK_DIV 257
|
||||
#define CLKID_SPICC1_SCLK_SEL 259
|
||||
#define CLKID_SPICC1_SCLK_DIV 260
|
||||
|
||||
#define NR_CLKS 256
|
||||
#define NR_CLKS 262
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/g12a-clkc.h>
|
||||
|
|
|
|||
|
|
@ -2613,19 +2613,12 @@ static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
|
|||
static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
|
||||
static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
|
||||
static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
|
||||
static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
|
||||
static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
|
||||
|
||||
static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
|
||||
static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
|
||||
static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
|
||||
static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
|
||||
static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
|
||||
static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
|
||||
static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
|
||||
static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
|
||||
static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
|
||||
static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
|
||||
static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
|
||||
static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
|
||||
static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
|
||||
static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
|
||||
|
|
@ -2680,6 +2673,16 @@ static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
|
|||
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
|
||||
static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
|
||||
|
||||
/* AIU gates */
|
||||
static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
|
||||
static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
|
||||
static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
|
||||
static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
|
||||
static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
|
||||
static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
|
||||
static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
|
||||
static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
|
||||
|
||||
/* Array of all clocks provided by this provider */
|
||||
|
||||
static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
||||
|
|
@ -3100,6 +3103,7 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
|
|||
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &gxbb_hdmi.hw,
|
||||
[CLKID_ACODEC] = &gxl_acodec.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
|
|
@ -3491,6 +3495,7 @@ static struct clk_regmap *const gxl_clk_regmaps[] = {
|
|||
&gxl_hdmi_pll_od,
|
||||
&gxl_hdmi_pll_od2,
|
||||
&gxl_hdmi_pll_dco,
|
||||
&gxl_acodec,
|
||||
};
|
||||
|
||||
static const struct meson_eeclkc_data gxbb_clkc_data = {
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@
|
|||
#define CLKID_HDMI_SEL 203
|
||||
#define CLKID_HDMI_DIV 204
|
||||
|
||||
#define NR_CLKS 206
|
||||
#define NR_CLKS 207
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
|
|
|||
|
|
@ -2605,14 +2605,6 @@ static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
|
|||
static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
|
||||
static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
|
||||
static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
|
||||
static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
|
||||
static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
|
||||
static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
|
||||
static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
|
||||
static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
|
||||
static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
|
||||
static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
|
||||
static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
|
||||
static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
|
||||
static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
|
||||
static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
|
||||
|
|
@ -2659,6 +2651,19 @@ static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
|
|||
static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
|
||||
static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
|
||||
|
||||
/* AIU gates */
|
||||
#define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
|
||||
MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
|
||||
|
||||
static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
|
||||
static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
|
||||
static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
|
||||
static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
|
||||
static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
|
||||
static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
|
||||
static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
|
||||
static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
|
||||
|
||||
/* Always On (AO) domain gates */
|
||||
|
||||
static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ config CLK_RENESAS
|
|||
select CLK_R8A7791 if ARCH_R8A7791 || ARCH_R8A7793
|
||||
select CLK_R8A7792 if ARCH_R8A7792
|
||||
select CLK_R8A7794 if ARCH_R8A7794
|
||||
select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951 || ARCH_R8A7795
|
||||
select CLK_R8A7795 if ARCH_R8A77950 || ARCH_R8A77951
|
||||
select CLK_R8A77960 if ARCH_R8A77960
|
||||
select CLK_R8A77961 if ARCH_R8A77961
|
||||
select CLK_R8A77965 if ARCH_R8A77965
|
||||
|
|
@ -161,6 +161,7 @@ config CLK_RCAR_GEN3_CPG
|
|||
config CLK_RCAR_USB2_CLOCK_SEL
|
||||
bool "Renesas R-Car USB2 clock selector support"
|
||||
depends on ARCH_RENESAS || COMPILE_TEST
|
||||
select RESET_CONTROLLER
|
||||
help
|
||||
This is a driver for R-Car USB2 clock selector
|
||||
|
||||
|
|
|
|||
|
|
@ -44,6 +44,7 @@ enum clk_ids {
|
|||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
|
|
@ -70,6 +71,12 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A7795_CLK_RPC),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -242,6 +249,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
|
|||
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
|
||||
DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@ enum clk_ids {
|
|||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
|
|
@ -72,6 +73,12 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A7796_CLK_RPC),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -105,6 +112,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
|
|||
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
|
|
@ -132,6 +140,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
|
|||
DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
|
||||
DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR),
|
||||
DEF_MOD("cmt3", 300, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A7796_CLK_R),
|
||||
|
|
@ -215,6 +224,7 @@ static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
|
|||
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
|
||||
DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@ enum clk_ids {
|
|||
CLK_S3,
|
||||
CLK_SDSRC,
|
||||
CLK_SSPSRC,
|
||||
CLK_RPCSRC,
|
||||
CLK_RINT,
|
||||
|
||||
/* Module Clocks */
|
||||
|
|
@ -68,6 +69,12 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
|
|||
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
|
||||
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
|
||||
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
|
||||
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
|
||||
|
||||
DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
|
||||
CLK_RPCSRC),
|
||||
DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
|
||||
R8A77965_CLK_RPC),
|
||||
|
||||
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
|
||||
|
||||
|
|
@ -99,7 +106,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
|
|||
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
|
||||
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
|
||||
|
||||
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
|
||||
DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
|
||||
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
|
||||
|
||||
|
|
@ -127,6 +135,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
|||
DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
|
||||
DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
|
||||
|
|
@ -215,6 +224,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
|
|||
DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
|
||||
DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
|
||||
DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
|
||||
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
|
||||
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
|
||||
|
|
|
|||
|
|
@ -105,6 +105,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
|
|||
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
|
||||
|
||||
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
|
||||
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
|
|
@ -135,6 +136,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
|
|||
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
|
||||
DEF_MOD("sceg-pub", 229, R8A77990_CLK_CR),
|
||||
|
||||
DEF_MOD("cmt3", 300, R8A77990_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77990_CLK_R),
|
||||
|
|
|
|||
|
|
@ -91,6 +91,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
|
|||
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
|
||||
|
||||
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
|
||||
DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
|
||||
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
|
||||
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
|
||||
|
||||
|
|
@ -122,6 +123,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
|
|||
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
|
||||
DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
|
||||
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
|
||||
DEF_MOD("cmt1", 302, R8A77995_CLK_R),
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#define USB20_CLKSET0 0x00
|
||||
|
|
@ -26,9 +27,16 @@
|
|||
#define CLKSET0_PRIVATE BIT(0)
|
||||
#define CLKSET0_EXTAL_ONLY (CLKSET0_INTCLK_EN | CLKSET0_PRIVATE)
|
||||
|
||||
static const struct clk_bulk_data rcar_usb2_clocks[] = {
|
||||
{ .id = "ehci_ohci", },
|
||||
{ .id = "hs-usb-if", },
|
||||
};
|
||||
|
||||
struct usb2_clock_sel_priv {
|
||||
void __iomem *base;
|
||||
struct clk_hw hw;
|
||||
struct clk_bulk_data clks[ARRAY_SIZE(rcar_usb2_clocks)];
|
||||
struct reset_control *rsts;
|
||||
bool extal;
|
||||
bool xtal;
|
||||
};
|
||||
|
|
@ -53,14 +61,32 @@ static void usb2_clock_sel_disable_extal_only(struct usb2_clock_sel_priv *priv)
|
|||
|
||||
static int usb2_clock_sel_enable(struct clk_hw *hw)
|
||||
{
|
||||
usb2_clock_sel_enable_extal_only(to_priv(hw));
|
||||
struct usb2_clock_sel_priv *priv = to_priv(hw);
|
||||
int ret;
|
||||
|
||||
ret = reset_control_deassert(priv->rsts);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(ARRAY_SIZE(priv->clks), priv->clks);
|
||||
if (ret) {
|
||||
reset_control_assert(priv->rsts);
|
||||
return ret;
|
||||
}
|
||||
|
||||
usb2_clock_sel_enable_extal_only(priv);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void usb2_clock_sel_disable(struct clk_hw *hw)
|
||||
{
|
||||
usb2_clock_sel_disable_extal_only(to_priv(hw));
|
||||
struct usb2_clock_sel_priv *priv = to_priv(hw);
|
||||
|
||||
usb2_clock_sel_disable_extal_only(priv);
|
||||
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(priv->clks), priv->clks);
|
||||
reset_control_assert(priv->rsts);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -119,6 +145,7 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
|
|||
struct usb2_clock_sel_priv *priv;
|
||||
struct clk *clk;
|
||||
struct clk_init_data init;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
|
|
@ -128,6 +155,15 @@ static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
memcpy(priv->clks, rcar_usb2_clocks, sizeof(priv->clks));
|
||||
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(priv->clks), priv->clks);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
priv->rsts = devm_reset_control_array_get(dev, true, false);
|
||||
if (IS_ERR(priv->rsts))
|
||||
return PTR_ERR(priv->rsts);
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
pm_runtime_get_sync(dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -51,9 +51,9 @@ static int rockchip_mmc_get_phase(struct clk_hw *hw)
|
|||
u16 degrees;
|
||||
u32 delay_num = 0;
|
||||
|
||||
/* See the comment for rockchip_mmc_set_phase below */
|
||||
/* Constant signal, no measurable phase shift */
|
||||
if (!rate)
|
||||
return -EINVAL;
|
||||
return 0;
|
||||
|
||||
raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
|
||||
|
||||
|
|
|
|||
|
|
@ -55,10 +55,6 @@
|
|||
|
||||
/* All the DRAM gates are exported */
|
||||
|
||||
/* Some more module clocks are exported */
|
||||
|
||||
#define CLK_MBUS 112
|
||||
|
||||
/* And the DSI and GPU module clock is exported */
|
||||
|
||||
#define CLK_NUMBER (CLK_GPU + 1)
|
||||
|
|
|
|||
|
|
@ -50,24 +50,8 @@ static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
|
|||
CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static struct ccu_common *sun50i_h6_de3_clks[] = {
|
||||
&mixer0_clk.common,
|
||||
&mixer1_clk.common,
|
||||
&wb_clk.common,
|
||||
|
||||
&bus_mixer0_clk.common,
|
||||
&bus_mixer1_clk.common,
|
||||
&bus_wb_clk.common,
|
||||
|
||||
&mixer0_div_clk.common,
|
||||
&mixer1_div_clk.common,
|
||||
&wb_div_clk.common,
|
||||
|
||||
&bus_rot_clk.common,
|
||||
&rot_clk.common,
|
||||
&rot_div_clk.common,
|
||||
};
|
||||
static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static struct ccu_common *sun8i_a83t_de2_clks[] = {
|
||||
&mixer0_clk.common,
|
||||
|
|
@ -81,6 +65,10 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
|
|||
&mixer0_div_a83_clk.common,
|
||||
&mixer1_div_a83_clk.common,
|
||||
&wb_div_a83_clk.common,
|
||||
|
||||
&bus_rot_clk.common,
|
||||
&rot_clk.common,
|
||||
&rot_div_a83_clk.common,
|
||||
};
|
||||
|
||||
static struct ccu_common *sun8i_h3_de2_clks[] = {
|
||||
|
|
@ -108,21 +96,42 @@ static struct ccu_common *sun8i_v3s_de2_clks[] = {
|
|||
&wb_div_clk.common,
|
||||
};
|
||||
|
||||
static struct ccu_common *sun50i_a64_de2_clks[] = {
|
||||
&mixer0_clk.common,
|
||||
&mixer1_clk.common,
|
||||
&wb_clk.common,
|
||||
|
||||
&bus_mixer0_clk.common,
|
||||
&bus_mixer1_clk.common,
|
||||
&bus_wb_clk.common,
|
||||
|
||||
&mixer0_div_clk.common,
|
||||
&mixer1_div_clk.common,
|
||||
&wb_div_clk.common,
|
||||
|
||||
&bus_rot_clk.common,
|
||||
&rot_clk.common,
|
||||
&rot_div_clk.common,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_MIXER0] = &mixer0_clk.common.hw,
|
||||
[CLK_MIXER1] = &mixer1_clk.common.hw,
|
||||
[CLK_WB] = &wb_clk.common.hw,
|
||||
[CLK_ROT] = &rot_clk.common.hw,
|
||||
|
||||
[CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw,
|
||||
[CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
|
||||
[CLK_BUS_WB] = &bus_wb_clk.common.hw,
|
||||
[CLK_BUS_ROT] = &bus_rot_clk.common.hw,
|
||||
|
||||
[CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
|
||||
[CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
|
||||
[CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
|
||||
[CLK_ROT_DIV] = &rot_div_a83_clk.common.hw,
|
||||
},
|
||||
.num = CLK_NUMBER_WITHOUT_ROT,
|
||||
.num = CLK_NUMBER_WITH_ROT,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
|
||||
|
|
@ -156,7 +165,7 @@ static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
|
|||
.num = CLK_NUMBER_WITHOUT_ROT,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
|
||||
static struct clk_hw_onecell_data sun50i_a64_de2_hw_clks = {
|
||||
.hws = {
|
||||
[CLK_MIXER0] = &mixer0_clk.common.hw,
|
||||
[CLK_MIXER1] = &mixer1_clk.common.hw,
|
||||
|
|
@ -179,9 +188,19 @@ static struct clk_hw_onecell_data sun50i_h6_de3_hw_clks = {
|
|||
static struct ccu_reset_map sun8i_a83t_de2_resets[] = {
|
||||
[RST_MIXER0] = { 0x08, BIT(0) },
|
||||
/*
|
||||
* For A83T, H3 and R40, mixer1 reset line is shared with wb, so
|
||||
* only RST_WB is exported here.
|
||||
* For V3s there's just no mixer1, so it also shares this struct.
|
||||
* Mixer1 reset line is shared with wb, so only RST_WB is
|
||||
* exported here.
|
||||
*/
|
||||
[RST_WB] = { 0x08, BIT(2) },
|
||||
[RST_ROT] = { 0x08, BIT(3) },
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun8i_h3_de2_resets[] = {
|
||||
[RST_MIXER0] = { 0x08, BIT(0) },
|
||||
/*
|
||||
* Mixer1 reset line is shared with wb, so only RST_WB is
|
||||
* exported here.
|
||||
* V3s doesn't have mixer1, so it also shares this struct.
|
||||
*/
|
||||
[RST_WB] = { 0x08, BIT(2) },
|
||||
};
|
||||
|
|
@ -190,13 +209,13 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
|
|||
[RST_MIXER0] = { 0x08, BIT(0) },
|
||||
[RST_MIXER1] = { 0x08, BIT(1) },
|
||||
[RST_WB] = { 0x08, BIT(2) },
|
||||
[RST_ROT] = { 0x08, BIT(3) },
|
||||
};
|
||||
|
||||
static struct ccu_reset_map sun50i_h6_de3_resets[] = {
|
||||
static struct ccu_reset_map sun50i_h5_de2_resets[] = {
|
||||
[RST_MIXER0] = { 0x08, BIT(0) },
|
||||
[RST_MIXER1] = { 0x08, BIT(1) },
|
||||
[RST_WB] = { 0x08, BIT(2) },
|
||||
[RST_ROT] = { 0x08, BIT(3) },
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
|
||||
|
|
@ -215,30 +234,20 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
|
|||
|
||||
.hw_clks = &sun8i_h3_de2_hw_clks,
|
||||
|
||||
.resets = sun8i_h3_de2_resets,
|
||||
.num_resets = ARRAY_SIZE(sun8i_h3_de2_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
|
||||
.ccu_clks = sun50i_a64_de2_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
|
||||
|
||||
.hw_clks = &sun50i_a64_de2_hw_clks,
|
||||
|
||||
.resets = sun8i_a83t_de2_resets,
|
||||
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
|
||||
.ccu_clks = sun8i_h3_de2_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
|
||||
|
||||
.hw_clks = &sun8i_h3_de2_hw_clks,
|
||||
|
||||
.resets = sun50i_a64_de2_resets,
|
||||
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun50i_h6_de3_clk_desc = {
|
||||
.ccu_clks = sun50i_h6_de3_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_de3_clks),
|
||||
|
||||
.hw_clks = &sun50i_h6_de3_hw_clks,
|
||||
|
||||
.resets = sun50i_h6_de3_resets,
|
||||
.num_resets = ARRAY_SIZE(sun50i_h6_de3_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
|
||||
.ccu_clks = sun8i_v3s_de2_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
|
||||
|
|
@ -249,6 +258,26 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
|
|||
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
|
||||
.ccu_clks = sun50i_a64_de2_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
|
||||
|
||||
.hw_clks = &sun50i_a64_de2_hw_clks,
|
||||
|
||||
.resets = sun50i_a64_de2_resets,
|
||||
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
|
||||
};
|
||||
|
||||
static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
|
||||
.ccu_clks = sun8i_h3_de2_clks,
|
||||
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
|
||||
|
||||
.hw_clks = &sun8i_h3_de2_hw_clks,
|
||||
|
||||
.resets = sun50i_h5_de2_resets,
|
||||
.num_resets = ARRAY_SIZE(sun50i_h5_de2_resets),
|
||||
};
|
||||
|
||||
static int sunxi_de2_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
|
|
@ -337,6 +366,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
|
|||
.compatible = "allwinner,sun8i-h3-de2-clk",
|
||||
.data = &sun8i_h3_de2_clk_desc,
|
||||
},
|
||||
{
|
||||
.compatible = "allwinner,sun8i-r40-de2-clk",
|
||||
.data = &sun8i_r40_de2_clk_desc,
|
||||
},
|
||||
{
|
||||
.compatible = "allwinner,sun8i-v3s-de2-clk",
|
||||
.data = &sun8i_v3s_de2_clk_desc,
|
||||
|
|
@ -347,11 +380,11 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
|
|||
},
|
||||
{
|
||||
.compatible = "allwinner,sun50i-h5-de2-clk",
|
||||
.data = &sun50i_a64_de2_clk_desc,
|
||||
.data = &sun50i_h5_de2_clk_desc,
|
||||
},
|
||||
{
|
||||
.compatible = "allwinner,sun50i-h6-de3-clk",
|
||||
.data = &sun50i_h6_de3_clk_desc,
|
||||
.data = &sun50i_h5_de2_clk_desc,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
|
|
|||
|
|
@ -143,5 +143,7 @@
|
|||
#define CLKID_CPU1_CLK 253
|
||||
#define CLKID_CPU2_CLK 254
|
||||
#define CLKID_CPU3_CLK 255
|
||||
#define CLKID_SPICC0_SCLK 258
|
||||
#define CLKID_SPICC1_SCLK 261
|
||||
|
||||
#endif /* __G12A_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -146,5 +146,6 @@
|
|||
#define CLKID_CTS_VDAC 201
|
||||
#define CLKID_HDMI_TX 202
|
||||
#define CLKID_HDMI 205
|
||||
#define CLKID_ACODEC 206
|
||||
|
||||
#endif /* __GXBB_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@
|
|||
#define CLK_AVS 109
|
||||
#define CLK_HDMI 110
|
||||
#define CLK_HDMI_DDC 111
|
||||
|
||||
#define CLK_MBUS 112
|
||||
#define CLK_DSI_DPHY 113
|
||||
#define CLK_GPU 114
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user