Commit Graph

2298 Commits

Author SHA1 Message Date
Thomas Gleixner
1b7efaa615 - Add sama5d2 support and rework the 32kHz clock handling (Alexandre Belloni)
- Add the high resolution support for SMP/SMT on the Ingenic timer (Zhou Yanjie)
 
 - Add support for i.MX TPM driver with ARM64 (Anson Huang)
 
 - Fix typo by replacing KHz to kHz (Geert Uytterhoeven)
 
 - Add 32kHz support by setting the minimum ticks to 5 on Nomadik MTU (Linus Walleij)
 
 - Replace HTTP links with HTTPS ones for security reasons (Alexander A. Klimov)
 
 - Add support for the Ingenic X1000 OST (Zhou Yanjie)
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAl8ZqeUACgkQqDIjiipP
 6E9tawf/UGUhEfB+VmH9w60NJlM0fC5a/TjVOb4yMjTZjjdyd4zMBHemF+dqMNnw
 wTr+S8U9QfvP4BDgg1hWV+vhAwxz2xkhR0cGtOQjck5322vZglGSmAVqTCAlQMoZ
 LNm98XeUYYVNMB+/+BHkf8F/nHV9vRo8sJg7UnvX/6RCykXFYXVP+P8LfkAU1MPt
 8vaRPCcyGnYXrgjDYY5M5qYudLNpFPrzr1yJDWdwWUliwH3T1X1FNogTdUo955qk
 wM+Hb4yPRuRufM+yATPsRedQypZFpoWFObuEMD2FaIw/LZVxV7D1tmw5KhL2V1tZ
 XSzNiJDEgri/4LaVzXKP7sVlQlZfDQ==
 =DXTp
 -----END PGP SIGNATURE-----

Merge tag 'timers-v5.9' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull clock event/surce driver changes from Daniel Lezcano:

  - Add sama5d2 support and rework the 32kHz clock handling (Alexandre Belloni)
  - Add the high resolution support for SMP/SMT on the Ingenic timer (Zhou Yanjie)
  - Add support for i.MX TPM driver with ARM64 (Anson Huang)
  - Fix typo by replacing KHz to kHz (Geert Uytterhoeven)
  - Add 32kHz support by setting the minimum ticks to 5 on Nomadik MTU (Linus Walleij)
  - Replace HTTP links with HTTPS ones for security reasons (Alexander A. Klimov)
  - Add support for the Ingenic X1000 OST (Zhou Yanjie)
2020-07-23 21:04:05 +02:00
周琰杰 (Zhou Yanjie)
ac756d05c4 dt-bindings: timer: Add Ingenic X1000 OST bindings.
Add the OST bindings for the X1000 SoC from Ingenic.

Tested-by: 周正 (Zhou Zheng) <sernia.zhou@foxmail.com>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200722171804.97559-2-zhouyanjie@wanyeetech.com
2020-07-23 16:58:09 +02:00
Hanks Chen
b07b616214 pinctrl: mediatek: update pinmux definitions for mt6779
Add devicetree bindings for Mediatek mt6779 SoC Pin Controller.

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Andy Teng <andy.teng@mediatek.com>
Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Link: https://lore.kernel.org/r/1595503197-15246-2-git-send-email-hanks.chen@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-23 15:22:09 +02:00
Arnd Bergmann
9e586c8431 Reset controller updates for v5.9
This tag moves the reset-simple header out of drivers/reset for use by
 drivers outside of drivers/reset, adds a .reset() callback to
 reset-simple, converts i.MX reset bindings to json-schema, fixes a
 compile warning in the reset-intel-gw driver, and replaces some HTTP
 links with HTTPS ones in comments.
 -----BEGIN PGP SIGNATURE-----
 
 iI0EABYIADUWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXxWSARcccC56YWJlbEBw
 ZW5ndXRyb25peC5kZQAKCRDVhaclGDdiwAP6AP4ld+W8CqwjEw+tkTVoCcGpE3v4
 rmeEao1MtXtttiG9bAEAl2y794/zu0cXI0UEYqbhuqDYG/z8uXoBRvTGEP7UqQc=
 =tScp
 -----END PGP SIGNATURE-----

Merge tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux into arm/drivers

Reset controller updates for v5.9

This tag moves the reset-simple header out of drivers/reset for use by
drivers outside of drivers/reset, adds a .reset() callback to
reset-simple, converts i.MX reset bindings to json-schema, fixes a
compile warning in the reset-intel-gw driver, and replaces some HTTP
links with HTTPS ones in comments.

* tag 'reset-for-v5.9' of git://git.pengutronix.de/pza/linux:
  reset: Replace HTTP links with HTTPS ones
  reset: intel: fix a compile warning about REG_OFFSET redefined
  dt-bindings: reset: Convert i.MX7 reset to json-schema
  dt-bindings: reset: Convert i.MX reset to json-schema
  reset: simple: Add reset callback
  reset: Move reset-simple header out of drivers/reset

Link: https://lore.kernel.org/r/b718f052e38abbaac599d80645376b75e54aa5bd.camel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22 22:34:14 +02:00
Lars Povlsen
39c8378a1c dt-bindings: clock: sparx5: Add bindings include file
The Sparx5 support 9 different clock outputs. This include file has
defines for each supported clock ordinal.

Link: https://lore.kernel.org/r/20200615133242.24911-8-lars.povlsen@microchip.com
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22 22:28:45 +02:00
Arnd Bergmann
d27895a122 i.MX device tree update for 5.9:
- New board support: Protonic PRTI6Q/WD2/VT7/RVT and MYiR MYS-6ULX SBC.
 - Update IIM, OCOTP and SD/MMC device node name to match .yaml bindings.
 - Make tempmon node as child of anatop node according to hardware
   architecture.
 - The vf610-zii device update: configure fiber port to 1000BaseX, add
   switch watchdog, MDIO speed and preamble.
 - A series from Fabio Estevam to update imx6qdl-sabresd and
   imx6q-tbs2910 for using MDIO node and reset-assert-us.
 - Align L2 cache-controller device node name with .yaml schema.
 - Enable SATA support for imx6qp-sabreauto and imx6qp-sabresd board.
 - A series of patches from Shengjiu Wang to enable various audio
   support on i.MX6 devices.
 - Add Gateworks System Controller support for imx6qdl-gw devices.
 - Change default #pwm-cells setting to <3> in the SoC dtsi files.
 - Other small random changes.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl8VVgcUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM7azwf+KzAukegArKtAmsbAnYNKYztXXifW
 6Hc3+hv2mfUtsGfHPSUJJ5MhEW52xAbcXnYETUkmoWe1W1zIxrNNWvBUm4nPF5os
 0cO8tjk4cE4CYDnsl8sBSqT55sd3ke61I+j9q0NAQNyX9OlmZ3kfm8yw0yIsxTKp
 /FzoLmOeRzhVKHdZczuJ9Ts4kFyf3XtQrrN1UTbu715KdIbbsrJtXQ74ADBCnjfX
 8RUm3Y5XIaPcF4z2U8reMsbHCF120ENIfGwFRNo/Odx+1OVo1IrDB1+f/SP9ZP0T
 6+iKvfSS4RavzB1tvLdJ2/911t7qtqsneU33kwQKL0wrFZsT4ih42uBfpw==
 =1hHY
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree update for 5.9:

- New board support: Protonic PRTI6Q/WD2/VT7/RVT and MYiR MYS-6ULX SBC.
- Update IIM, OCOTP and SD/MMC device node name to match .yaml bindings.
- Make tempmon node as child of anatop node according to hardware
  architecture.
- The vf610-zii device update: configure fiber port to 1000BaseX, add
  switch watchdog, MDIO speed and preamble.
- A series from Fabio Estevam to update imx6qdl-sabresd and
  imx6q-tbs2910 for using MDIO node and reset-assert-us.
- Align L2 cache-controller device node name with .yaml schema.
- Enable SATA support for imx6qp-sabreauto and imx6qp-sabresd board.
- A series of patches from Shengjiu Wang to enable various audio
  support on i.MX6 devices.
- Add Gateworks System Controller support for imx6qdl-gw devices.
- Change default #pwm-cells setting to <3> in the SoC dtsi files.
- Other small random changes.

* tag 'imx-dt-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (43 commits)
  ARM: dts: vf610-zii-ssmb-spu3: Add node for switch watchdog
  ARM: dts: vf610-zii-ssmb-dtu: Add no-sdio/no-sd properties
  ARM: dts: imx6q-tbs2910: Pass reset-assert-us
  ARM: dts: imx6q-tbs2910: Add an mdio node
  ARM: dts: imx6qdl-sabresd: Pass reset-assert-us
  ARM: dts: imx6qdl-sabresd: Add an mdio node
  ARM: dts: imx6qdl-gw: add Gateworks System Controller support
  ARM: dts: imx6ull: add MYiR MYS-6ULX SBC
  ARM: dts: vf610-zii-spb4: Add node for switch watchdog
  ARM: dts: colibri-imx6: remove pinctrl-names orphan
  ARM: dts: imx: default to #pwm-cells = <3> in the SoC dtsi files
  ARM: dts: vf610-zii-scu4-aib: Configure fibre ports to 1000BaseX
  ARM: dts: vf610-zii-dev-rev-c: Configure fiber port to 1000BaseX
  ARM: dts: ZII: update MDIO speed and preamble
  ARM: dts: vfxxx: Add node for CAAM
  ARM: dts: imx6qp-sabresd: enable sata
  ARM: dts: imx6qp-sabreauto: enable sata
  ARM: dts: add Protonic RVT board
  ARM: dts: add Protonic VT7 board
  ARM: dts: add Protonic WD2 board
  ...

Link: https://lore.kernel.org/r/20200720085536.24138-3-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22 21:46:22 +02:00
Jonathan Cameron
d0d7c5845e Merge branch 'ib-5.8-jz47xx-ts' into HEAD
Immutable branch may be needed in input for a joystick set that is
dependent on it.
2020-07-22 14:36:31 +01:00
Cristian Ciocaltea
fac1d443a2 dt-bindings: reset: Add binding constants for Actions S500 RMU
Add device tree binding constants for Actions Semi S500 SoC Reset
Management Unit (RMU).

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/daf615160b3be9f38dcf7926cc82128c9c2d73e3.1593788312.git.cristian.ciocaltea@gmail.com
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21 01:50:46 -07:00
Cristian Ciocaltea
1a4ae4138f dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
Add the missing APB, DMAC and GPIO clock bindings constants for
Actions Semi S500 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Link: https://lore.kernel.org/r/67112af4f5bc0cc5e70ce8410feb369cc72972b8.1593788312.git.cristian.ciocaltea@gmail.com
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-21 01:50:46 -07:00
Stephen Boyd
63e95849a7 Merge branch 'clk-imx' into clk-next
* clk-imx:
  clk: imx: vf610: add CAAM clock
  clk: imx8mp: add mu root clk
2020-07-21 01:03:16 -07:00
Stephen Boyd
b396b3d206 Merge branch 'clk-amlogic' into clk-next
* clk-amlogic:
  clk: meson: meson8b: add the vclk2_en gate clock
  clk: meson: meson8b: add the vclk_en gate clock
  clk: meson: meson8b: Drop CLK_IS_CRITICAL from fclk_div2
  clk: meson: g12a: Add support for NNA CLK source clocks
  dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
2020-07-21 01:01:11 -07:00
Stephen Boyd
fca1484576 Merge branch 'clk-renesas' into clk-next
* clk-renesas:
  clk: renesas: cpg-mssr: Add r8a774e1 support
  dt-bindings: clock: renesas,cpg-mssr: Document r8a774e1
  clk: renesas: Add r8a774e1 CPG Core Clock Definitions
  dt-bindings: power: Add r8a774e1 SYSC power domain definitions
2020-07-21 00:57:38 -07:00
Stephen Boyd
73d6bd7acb Merge branch 'clk-qcom' into clk-next
* clk-qcom:
  clk: qcom: gcc: Make disp gpll0 branch aon for sc7180/sdm845
  ipq806x: gcc: add support for child probe
  clk: qcom: msm8996: Make symbol 'cpu_msm8996_clks' static
  clk: qcom: ipq8074: Add correct index for PCIe clocks
2020-07-21 00:55:21 -07:00
Sivaprakash Murugesan
044f507dc0 clk: qcom: ipq8074: Add correct index for PCIe clocks
The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC,
GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group.

Move them to the gcc clock group.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1594877570-9280-1-git-send-email-sivaprak@codeaurora.org
Fixes: e7fb524cfc ("dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-20 17:38:46 -07:00
Artur Rojek
842247203c dt-bindings: iio/adc: Add touchscreen idx for JZ47xx SoC ADC
Introduce support for touchscreen channels found in JZ47xx SoCs.

Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
Tested-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-07-20 10:27:46 +01:00
Alexander A. Klimov
ffebbecaaa reset: Replace HTTP links with HTTPS ones
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Deterministic algorithm:
For each file:
  If not .svg:
    For each line:
      If doesn't contain `\bxmlns\b`:
        For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
	  If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
            If both the HTTP and HTTPS versions
            return 200 OK and serve the same content:
              Replace HTTP with HTTPS.

Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-07-20 11:27:12 +02:00
Kishon Vijay Abraham I
b766e3b0d5 arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-07-17 10:35:07 +03:00
Alexander A. Klimov
303d6f62eb arm64: dts: ti: k3-*: Replace HTTP links with HTTPS ones
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.

Deterministic algorithm:
For each file:
  If not .svg:
    For each line:
      If doesn't contain `\bxmlns\b`:
        For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
	  If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
            If both the HTTP and HTTPS versions
            return 200 OK and serve the same content:
              Replace HTTP with HTTPS.

Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-07-17 10:23:48 +03:00
Laurent Pinchart
ef9303fdf4 dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA
The ZynqMP includes the DisplayPort subsystem with its own DMA engine
called DPDMA. The DPDMA IP comes with 6 individual channels
(4 for display, 2 for audio). This documentation describes DT bindings
of DPDMA.

Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200717013337.24122-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-17 11:37:59 +05:30
Dan Murphy
5c7f8ffe74 dt: bindings: Add multicolor class dt bindings documention
Add DT bindings for the LEDs multicolor class framework.
Add multicolor ID to the color ID list for device tree bindings.

CC: Rob Herring <robh@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Jacek Anaszewski <jacek.anaszewski@gmail.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
2020-07-15 19:33:04 +02:00
Marian-Cristian Rotariu
ef1c992428 clk: renesas: Add r8a774e1 CPG Core Clock Definitions
Add all RZ/G2H Clock Pulse Generator Core Clock Outputs, as listed in
Table 11.2 ("List of Clocks [RZ/G2H]") of the RZ/G2H Hardware User's
Manual.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594138692-16816-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-07-13 10:18:05 +02:00
Marian-Cristian Rotariu
e24779649c dt-bindings: power: Add r8a774e1 SYSC power domain definitions
This patch adds power domain indices for the RZ/G2H (r8a774e1) SoC.

Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/1594138692-16816-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-07-13 10:18:05 +02:00
Stephen Boyd
96310398fc Merge branch 'clk-qcom' into clk-next
* clk-qcom:
  clk: qcom: smd: Add support for MSM8992/4 rpm clocks
  clk: qcom: ipq8074: Add missing clocks for pcie
  dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
2020-07-11 09:27:58 -07:00
Konrad Dybcio
b429784499 clk: qcom: smd: Add support for MSM8992/4 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992,
MSM8994 (and APQ variants) for clients to vote on.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200623230018.303776-1-konradybcio@gmail.com
[sboyd@kernel.org: Fixed up binding numbers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:19:24 -07:00
Sivaprakash Murugesan
e7fb524cfc dt-bindings: clock: qcom: ipq8074: Add missing bindings for PCIe
Add missing clock bindings for PCIe port0 of ipq8074.

Co-developed-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@codeaurora.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1593940680-2363-4-git-send-email-sivaprak@codeaurora.org
[sboyd@kernel.org: Clean up commit text subject]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-11 09:10:52 -07:00
Chao Hao
349b00c9c0 dt-bindings: mediatek: Add bindings for MT6779
This patch adds description for MT6779 IOMMU.

MT6779 has two iommus, they are mm_iommu and apu_iommu which
both use ARM Short-Descriptor translation format.

In addition, mm_iommu and apu_iommu are two independent HW instance
, we need to set them separately.

The MT6779 IOMMU hardware diagram is as below, it is only a brief
diagram about iommu, it don't focus on the part of smi_larb, so
I don't describe the smi_larb detailedly.

			     EMI
			      |
	   --------------------------------------
	   |					|
        MM_IOMMU                            APU_IOMMU
	   |					|
       SMI_COMMOM-----------		     APU_BUS
          |		   |			|
    SMI_LARB(0~11)         |	                |
	  |		   |			|
	  |		   |		   --------------
	  |		   |		   |	 |	|
   Multimedia engine	  CCU		  VPU   MDLA   EMDA

All the connections are hardware fixed, software can not adjust it.

Signed-off-by: Chao Hao <chao.hao@mediatek.com>
Reviewed-by: Rob Herring <robh+dt@kernel.org>
Link: https://lore.kernel.org/r/20200703044127.27438-2-chao.hao@mediatek.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2020-07-10 16:13:10 +02:00
Drew Fustini
27c90e5e48 ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2
Increase #pinctrl-cells to 2 so that mux and conf be kept separate. This
requires the AM33XX_PADCONF macro in omap.h to also be modified to keep pin
conf and pin mux values separate.

Signed-off-by: Drew Fustini <drew@beagleboard.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Link: https://lore.kernel.org/r/20200701013320.130441-3-drew@beagleboard.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07 12:58:20 +02:00
Mark Brown
8cc31dc941
Merge series "regulator: mt6397: Implement of_map_mode regulator_desc function" from Anand K Mistry <amistry@google.com>:
This patchset adds support for being able to change regulator modes for
the mt6397 regulator. This is needed to allow the voltage scaling
support in the MT8173 SoC to be used on the elm (Acer Chromebook R13)
and hana (several Lenovo Chromebooks) devices.

Without a of_map_mode implementation, the regulator-allowed-modes
devicetree field is skipped, and attempting to change the regulator mode
results in an error:
[    1.439165] vpca15: mode operation not allowed

Changes in v2:
- Introduce constants in dt-bindings
- Improve conditional readability

Anand K Mistry (4):
  regulator: mt6397: Move buck modes into header file
  dt-bindings: regulator: mt6397: Document valid modes
  regulator: mt6397: Implement of_map_mode
  arm64: dts: mediatek: Update allowed mt6397 regulator modes for elm
    boards

 .../bindings/regulator/mt6397-regulator.txt     |  3 +++
 arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi    |  4 +++-
 drivers/regulator/mt6397-regulator.c            | 17 ++++++++++++++---
 .../regulator/mediatek,mt6397-regulator.h       | 15 +++++++++++++++
 4 files changed, 35 insertions(+), 4 deletions(-)
 create mode 100644 include/dt-bindings/regulator/mediatek,mt6397-regulator.h

--
2.27.0.212.ge8ba1cc988-goog

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
2020-07-02 16:45:49 +01:00
Anand K Mistry
6c8b65950b
regulator: da9211: Move buck modes into header file
This will allow device trees to make use of these constants.

Signed-off-by: Anand K Mistry <amistry@google.com>
Link: https://lore.kernel.org/r/20200702131350.1.I96e67ab7b4568287eb939e8a572cbc03e87f1aa0@changeid
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-02 16:20:57 +01:00
Anand K Mistry
1c537b2d72
regulator: mt6397: Move buck modes into header file
This will allow device trees to make use of these constants.

Signed-off-by: Anand K Mistry <amistry@google.com>
Link: https://lore.kernel.org/r/20200702162231.v2.1.Icf69e2041b1af4548347018186c3ba6310f53e66@changeid
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-02 15:25:45 +01:00
Anurag Kumar Vulisha
cea0f76a48 dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
Processing System Gigabit Transceiver which provides PHY capabilities to
USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.

Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29 18:48:00 +05:30
Stephen Boyd
12ef3933b4 Merge branch 'clk-bcm' into clk-next
- Make defines for bcm63xx-gate clks to use in DT
 - Support gate clks on BCM6318 SoCs
 - Add HDMI clks for BCM2711 SoCs
 - Support BCM2711 SoC firmware clks

* clk-bcm: (42 commits)
  clk: bcm: dvp: Add missing module informations
  clk: bcm: rpi: Remove the quirks for the CPU clock
  clk: bcm2835: Don't cache the PLLB rate
  clk: bcm2835: Allow custom CCF flags for the PLLs
  Revert "clk: bcm2835: remove pllb"
  clk: bcm: rpi: Give firmware clocks a name
  clk: bcm: rpi: Discover the firmware clocks
  clk: bcm: rpi: Add an enum for the firmware clocks
  clk: bcm: rpi: Add DT provider for the clocks
  clk: bcm: rpi: Make the PLLB registration function return a clk_hw
  clk: bcm: rpi: Split pllb clock hooks
  clk: bcm: rpi: Rename is_prepared function
  clk: bcm: rpi: Pass the clocks data to the firmware function
  clk: bcm: rpi: Add clock id to data
  clk: bcm: rpi: Create a data structure for the clocks
  clk: bcm: rpi: Use CCF boundaries instead of rolling our own
  clk: bcm: rpi: Make sure the clkdev lookup is removed
  clk: bcm: rpi: Switch to clk_hw_register_clkdev
  clk: bcm: rpi: Remove pllb_arm_lookup global pointer
  clk: bcm: rpi: Make sure pllb_arm is removed
  ...
2020-06-26 11:58:51 -07:00
Stephen Boyd
7aae3c161e Merge branch 'clk-vc5' into clk-next
* clk-vc5:
  clk: vc5: Enable addition output configurations of the Versaclock
  dt: Add additional option bindings for IDT VersaClock
  clk: vc5: Allow Versaclock driver to support multiple instances
2020-06-23 12:12:43 -07:00
Andrey Smirnov
018e430834 clk: imx: vf610: add CAAM clock
According to Vybrid Security RM, CCM_CCGR11[CG176] can be used to gate
CAAM ipg clock.

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-imx@nxp.com
Tested-by: Chris Healy <cphealy@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-06-23 15:10:05 +08:00
Adam Ford
34662f6e30 dt: Add additional option bindings for IDT VersaClock
The VersaClock driver now supports some additional bindings to support
child nodes which can configure optional settings like mode, voltage
and slew.

This patch updates the binding document to describe what is available
in the driver.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200603154329.31579-2-aford173@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 19:04:58 -07:00
Stephen Boyd
ef01ab612b Merge branch 'clk-qcom' into clk-next
- Enable CPU clks on Qualcomm IPQ6018 SoCs

* clk-qcom:
  clk: qcom: smd: Add support for MSM8936 rpm clocks
  dt-bindings: clock: rpmcc: Document MSM8936 compatible
  clk: qcom: smd: Add support for SDM660 rpm clocks
  clk: qcom: Add ipq6018 apss clock controller
  clk: qcom: Add DT bindings for ipq6018 apss clock controller
  clk: qcom: Add ipq apss pll driver
  dt-bindings: clock: add ipq6018 a53 pll compatible
2020-06-22 19:02:18 -07:00
Vincent Knecht
59390282b7 clk: qcom: smd: Add support for MSM8936 rpm clocks
Add missing definition of rpm clk for msm8936 soc (also used by msm8939)

Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20200613072745.1249003-2-vincent.knecht@mailoo.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 19:01:25 -07:00
Konrad Dybcio
b608013ac5 clk: qcom: smd: Add support for SDM660 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on
SDM630/660 (and APQ variants) for clients to vote on.

Signed-off-by: Konrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200622090252.36568-1-konradybcio@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 02:11:38 -07:00
Sivaprakash Murugesan
49bcaef86e clk: qcom: Add DT bindings for ipq6018 apss clock controller
Add dt-binding for ipq6018 apss clock controller

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1592800092-20533-4-git-send-email-sivaprak@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-22 00:21:59 -07:00
Dinh Nguyen
c2710fdf93 dt-bindings: agilex: add NAND_X_CLK and NAND_ECC_CLK
Add the NAND_X_CLK and NAND_ECC_CLK clocks.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20200616202417.14376-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 19:27:33 -07:00
Álvaro Fernández Rojas
f3cd8c96a9 mips: bmips: add BCM63268 clock definitions
Add header with BCM63268 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200615090231.2932696-8-noltari@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:03:24 -07:00
Álvaro Fernández Rojas
ad31e793f2 mips: bmips: add BCM6368 clock definitions
Add header with BCM6368 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200615090231.2932696-7-noltari@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:03:24 -07:00
Álvaro Fernández Rojas
fb8fb3f13f mips: bmips: add BCM6362 clock definitions
Add header with BCM6362 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200615090231.2932696-6-noltari@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:03:23 -07:00
Álvaro Fernández Rojas
d3499bda4e mips: bmips: add BCM6358 clock definitions
Add header with BCM6358 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200615090231.2932696-5-noltari@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:03:23 -07:00
Álvaro Fernández Rojas
92cd8bb27a mips: bmips: add BCM6328 clock definitions
Add header with BCM6328 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200615090231.2932696-4-noltari@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:03:23 -07:00
Álvaro Fernández Rojas
020c89c5a9 mips: bmips: add BCM6318 clock definitions
Add header with BCM6318 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200615090231.2932696-3-noltari@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:03:23 -07:00
Álvaro Fernández Rojas
c7f03eea07 mips: bmips: add BCM3368 clock definitions
Add header with BCM3368 definitions in order to be able to include it from
device tree files.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Link: https://lore.kernel.org/r/20200615090231.2932696-2-noltari@gmail.com
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-06-19 17:03:23 -07:00
Dmitry Shmidt
df06230106 dt-bindings: clk: g12a-clkc: Add NNA CLK Source clock IDs
This adds the Neural Network Accelerator IP source clocks.

Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200610083012.5024-2-narmstrong@baylibre.com
2020-06-19 17:16:09 +02:00
Jishnu Prakash
d1492bbd47 iio: adc: Add PMIC7 ADC bindings
Add documentation for PMIC7 ADC peripheral.
For the PMIC7-type PMICs, ADC peripheral is present in HW for the
following PMICs: PMK8350, PM8350, PM8350b, PMR735a and PMR735b.
Of these, only the ADC peripheral on PMK8350 is exposed directly to SW.
If SW needs to communicate with ADCs on other PMICs, it specifies the
PMIC to PMK8350 through the newly added SID register and communication
between PMK8350 ADC and other PMIC ADCs is carried out through
PBS(Programmable Boot Sequence) at the firmware level.

In addition, add definitions for ADC channels and virtual channel
definitions (combination of ADC channel number and PMIC SID number)
per PMIC, to be used by ADC clients for PMIC7.

Signed-off-by: Jishnu Prakash <jprakash@codeaurora.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2020-06-14 11:49:18 +01:00
Linus Torvalds
2dca74a40e - qcom :
new controller driver for IPCC
      reorg the of_device data
      add support for ipq6018 platform
 - spreadtrum:
      new sprd controller driver
 - imx:
      implement suspend/resume PM support
 - Misc :
      make pcc driver struct as static
      fix return value in imx_mu_scu
      disable clock before bailout in imx probe
      remove duplicate error mssg in zynqmp probe
      fix header size in imx.scu
      check for null instead of is-err in zynqmp
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEE6EwehDt/SOnwFyTyf9lkf8eYP5UFAl7hrXUACgkQf9lkf8eY
 P5U+9g//TWG3xf8pTEDkKq5LDQbq2K58GeplYbS1M0dfF6kMQsl9jdPMh7F/8kdO
 fBE1yAeVQrv+uiL7TNdlM4AyfmFDO2if8snhvvLZD61LfTBzAQGfm48oz3zB7n3r
 f9pyrnCXvjYutQ4TpNT3WBOuuJSNLHcyfmJwhkpdLQYQiSywOhP+LAKrw3LMwaIk
 0/5LkixC1IuPOdShTRJnkR2WA4fZ0jhUFbZmP0OwmZZc4I0V/CsQzeh7DqZyCnak
 zcOaUg8bfOPGlPQVo4MHJpFlC/irIjPxD/TXPVftwHHB2Zz+g0u2uSC9mZvKdszW
 vUDGtywP64arcsyuCuDC1C/WVww30WiPhIT08MInbbNtsdMaPPdVJrnyQzY53xqo
 ZfFDZJ+F9K11xi2xU5EUh5KwWV3yQvx7Y2c5Y1G67Vu73jryvR5aPkCCCdRgL9Pv
 qe3ux5iMWK5XrnKm7UJ6kUxcEyhiP/ReKmozsnYpQzRzDlG3v8Gjghr6/tTjEV60
 At/f5zPn1GlX8kkkAakgORTHQ94MfsMrYh1CMY49P/ICntGKM3WYv9YGv1sDhxbn
 ih2G5VzngQtffnAQLyPsTGvuRLxFL1TEoVpI7/1OQq/ReksFxjN58X+Vc0W9PA7a
 mzhZROc/4KatjQNYx3YPejYWL9e9WqGecKRzO4TaxiDTElhgWvE=
 =FpYp
 -----END PGP SIGNATURE-----

Merge tag 'mailbox-v5.8' of git://git.linaro.org/landing-teams/working/fujitsu/integration

Pull mailbox updates from Jassi Brar:
 "qcom:
   - new controller driver for IPCC
   - reorg the of_device data
   - add support for ipq6018 platform

  spreadtrum:
   - new sprd controller driver

  imx:
   - implement suspend/resume PM support

  misc:
   - make pcc driver struct static
   - fix return value in imx_mu_scu
   - disable clock before bailout in imx probe
   - remove duplicate error mssg in zynqmp probe
   - fix header size in imx.scu
   - check for null instead of is-err in zynqmp"

* tag 'mailbox-v5.8' of git://git.linaro.org/landing-teams/working/fujitsu/integration:
  mailbox: qcom: Add ipq6018 apcs compatible
  mailbox: qcom: Add clock driver name in apcs mailbox driver data
  dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block
  mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flag
  mailbox: imx: Add runtime PM callback to handle MU clocks
  mailbox: imx: Add context save/restore for suspend/resume
  MAINTAINERS: Add entry for Qualcomm IPCC driver
  mailbox: Add support for Qualcomm IPCC
  dt-bindings: mailbox: Add devicetree binding for Qcom IPCC
  mailbox: zynqmp-ipi: Fix NULL vs IS_ERR() check in zynqmp_ipi_mbox_probe()
  mailbox: imx-mailbox: fix scu msg header size check
  mailbox: sprd: Add Spreadtrum mailbox driver
  dt-bindings: mailbox: Add the Spreadtrum mailbox documentation
  mailbox: ZynqMP IPI: Delete an error message in zynqmp_ipi_probe()
  mailbox: imx: Disable the clock on devm_mbox_controller_register() failure
  mailbox: imx: Fix return in imx_mu_scu_xlate()
  mailbox: imx: Support runtime PM
  mailbox: pcc: make pcc_mbox_driver static
2020-06-11 12:42:14 -07:00
Linus Torvalds
6f630784cc This time around we have 4 lines of diff in the core framework, removing a
function that isn't used anymore. Otherwise the main new thing for the common
 clk framework is that it is selectable in the Kconfig language now. Hopefully
 this will let clk drivers and clk consumers be testable on more than the
 architectures that support the clk framework. The goal is to introduce some
 Kunit tests for the framework.
 
 Outside of the core framework we have the usual set of various driver updates
 and non-critical fixes. The dirstat shows that the new Baikal-T1 driver is the
 largest addition this time around in terms of lines of code. After that the x86
 (Intel), Qualcomm, and Mediatek drivers introduce many lines to support new or
 upcoming SoCs. After that the dirstat shows the usual suspects working on their
 SoC support by fixing minor bugs, correcting data and converting some of their
 DT bindings to YAML.
 
 Core:
  - Allow the COMMON_CLK config to be selectable
 
 New Drivers:
  - Clk driver for Baikal-T1 SoCs
  - Mediatek MT6765 clock support
  - Support for Intel Agilex clks
  - Add support for X1830 and X1000 Ingenic SoC clk controllers
  - Add support for the new Renesas RZ/G1H (R8A7742) SoC
  - Add support for Qualcomm's MSM8939 Generic Clock Controller
 
 Updates:
  - Support IDT VersaClock 5P49V5925
  - Bunch of updates for HSDK clock generation unit (CGU) driver
  - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
  - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
  - Enable supply regulators for GPU gdscs on Qualcomm SoCs
  - Add support for Si5342, Si5344 and Si5345 chips
  - Support custom flags in Xilinx zynq firmware
  - Various small fixes to the Xilinx clk driver
  - A single minor rounding fix for the legacy Allwinner clock support
  - A few patches from Abel Vesa as preparation of adding audiomix clock support
    on i.MX
  - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and clk-pllv3
    drivers
  - Drop dependency on ARM64 for i.MX8M clock driver, to support aarch32 mode on
    aarch64 hardware
  - A series from Peng Fan to improve i.MX8M clock drivers, using composite
    clock for core and bus clk slice
  - Set a better parent clock for flexcan on i.MX6UL to support CiA102 defined
    bit rates
  - A couple changes for EMC frequency scaling on Tegra210
  - Support for CPU frequency scaling on Tegra20/Tegra30
  - New clk gate for CSI test pattern generator on Tegra210
  - Regression fixes for Samsung exynos542x and exynos5433 SoCs
  - Use of fallthrough; attribute for Samsung s3c24xx
  - Updates and fixup HDMI and video clocks on Meson8b
  - Fixup reset polarity on Meson8b
  - Fix GPU glitch free mux switch on Meson gx and g12
  - A minor fix for the currently unused suspend/resume handling on Renesas RZ/A1 and RZ/A2
  - Two more conversions of Renesas DT bindings to json-schema
  - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl7gEUgRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSUemxAAlQKzx0yMS3yx5twJ4RSFUvf3hf4OqyPp
 O46soqADk+l69Z4SUUBsMjt8el5Sqmm4d1j1Gpfmgp3ZlumHCQK+qGYp48IXbwRP
 Jlo5sKNlNL6yhCd+ixPn4j7W/HbpGs4cciWOXkGQtYEGjhHm3Wllhd9MqpL2YjLx
 gZW60NqWtOe1XeB4ILyYQGisNwAGDi5XuBeNvxG12H/LaGC1mwtBX9yoNAehr9bF
 peJ2XnO02zFo73OCyzIOkw1uY4u7ZtwPdHGhymoGeVlcBWO6KwKesNkHnji/Grlv
 wMbsGLoRV/i3PL3q5kZIDigo8sqZ9RUG+9piRAoiLM5AgkSypw3/q9T+ujTfZp8t
 kgvFha6bLZz31UFmr4lBJPTT5Q/hAoe1W6RB6HZkx7XNqUpsAS04SwkQztAqkJqZ
 9zlYJrXgLlP5qcNllJ6zvUWkMqtmIKW4ZkjYe4u84yk5Co7bX8DCYa+QOKCz+pV4
 IbjRT62OrX2ZlXJYwkLb4m1nhZ7tBzhzIRP1umL0ukhxdomK6ofSNPzbBF9+t1eR
 /ai2/Ch6L6WIwDINEp+chO67/dJaj5W3WNqGMCmVt37myW1kBjH3eg0YG4cp7NYZ
 /jSjdWczQy/8BgY5V1009MRXI4uyazQxBw+apDcIGezamOKBmuwjBcvkf1D0mL2x
 Y6OclK5ljsw=
 =nuG5
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This time around we have four lines of diff in the core framework,
  removing a function that isn't used anymore. Otherwise the main new
  thing for the common clk framework is that it is selectable in the
  Kconfig language now. Hopefully this will let clk drivers and clk
  consumers be testable on more than the architectures that support the
  clk framework. The goal is to introduce some Kunit tests for the
  framework.

  Outside of the core framework we have the usual set of various driver
  updates and non-critical fixes. The dirstat shows that the new
  Baikal-T1 driver is the largest addition this time around in terms of
  lines of code. After that the x86 (Intel), Qualcomm, and Mediatek
  drivers introduce many lines to support new or upcoming SoCs. After
  that the dirstat shows the usual suspects working on their SoC support
  by fixing minor bugs, correcting data and converting some of their DT
  bindings to YAML.

  Core:
   - Allow the COMMON_CLK config to be selectable

  New Drivers:
   - Clk driver for Baikal-T1 SoCs
   - Mediatek MT6765 clock support
   - Support for Intel Agilex clks
   - Add support for X1830 and X1000 Ingenic SoC clk controllers
   - Add support for the new Renesas RZ/G1H (R8A7742) SoC
   - Add support for Qualcomm's MSM8939 Generic Clock Controller

  Updates:
   - Support IDT VersaClock 5P49V5925
   - Bunch of updates for HSDK clock generation unit (CGU) driver
   - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
   - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
   - Enable supply regulators for GPU gdscs on Qualcomm SoCs
   - Add support for Si5342, Si5344 and Si5345 chips
   - Support custom flags in Xilinx zynq firmware
   - Various small fixes to the Xilinx clk driver
   - A single minor rounding fix for the legacy Allwinner clock support
   - A few patches from Abel Vesa as preparation of adding audiomix
     clock support on i.MX
   - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and
     clk-pllv3 drivers
   - Drop dependency on ARM64 for i.MX8M clock driver, to support
     aarch32 mode on aarch64 hardware
   - A series from Peng Fan to improve i.MX8M clock drivers, using
     composite clock for core and bus clk slice
   - Set a better parent clock for flexcan on i.MX6UL to support CiA102
     defined bit rates
   - A couple changes for EMC frequency scaling on Tegra210
   - Support for CPU frequency scaling on Tegra20/Tegra30
   - New clk gate for CSI test pattern generator on Tegra210
   - Regression fixes for Samsung exynos542x and exynos5433 SoCs
   - Use of fallthrough; attribute for Samsung s3c24xx
   - Updates and fixup HDMI and video clocks on Meson8b
   - Fixup reset polarity on Meson8b
   - Fix GPU glitch free mux switch on Meson gx and g12
   - A minor fix for the currently unused suspend/resume handling on
     Renesas RZ/A1 and RZ/A2
   - Two more conversions of Renesas DT bindings to json-schema
   - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits)
  clk: mediatek: Remove ifr{0,1}_cfg_regs structures
  clk: baikal-t1: remove redundant assignment to variable 'divider'
  clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"
  dt-bindings: clock: Add a missing include to MMP Audio Clock binding
  dt: Add bindings for IDT VersaClock 5P49V5925
  clk: vc5: Add support for IDT VersaClock 5P49V6965
  clk: Add Baikal-T1 CCU Dividers driver
  clk: Add Baikal-T1 CCU PLLs driver
  dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
  dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
  clk: mediatek: assign the initial value to clk_init_data of mtk_mux
  clk: mediatek: Add MT6765 clock support
  clk: mediatek: add mt6765 clock IDs
  dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
  dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
  dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
  CLK: HSDK: CGU: add support for 148.5MHz clock
  CLK: HSDK: CGU: support PLL bypassing
  CLK: HSDK: CGU: check if PLL is bypassed first
  clk: clk-si5341: Add support for the Si5345 series
  ...
2020-06-10 11:42:19 -07:00
Linus Torvalds
cf0c97f148 This is the bulk of pin control changes for the v5.8
kernel cycle.
 
 New drivers:
 
 - Intel Jasper Lake support.
 
 - NXP Freescale i.MX8DXL support.
 
 - Qualcomm SM8250 support.
 
 - Renesas R8A7742 SH-PFC support.
 
 Driver improvements:
 
 - Severe cleanup and modernization of the MCP23s08 driver.
 
 - Mediatek driver modularized.
 
 - Setting config supported in the Meson driver.
 
 - Wakeup support for the Broadcom BCM7211.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl7dZC4ACgkQQRCzN7AZ
 XXOEZg/9F4dCwXmMxMxbS1c7DSHxsJTEHYKDDgAZ0L36N2DHihpMGbVQFzEe9khK
 xeSS8M4ecACYzw3FJGESaEC+fmTZ7zxr60SR++iyJJptooKAmcA00d2M/4VQ4ggN
 P/nXFEsGJvQ7nNJSO95wXr5K8aVkQW7rjo1cnblXH0c9dYOp+ItyodIytKcdWeZ9
 QfWSovYd+Oqra0braxx+pM/iTFVf6eOoCFZ8gkXB35pORsZ4Vl/e8pXMHXc3wUUm
 S1b6e3fifLiEGANvCEXz47/f3lUmUY26FsCSCAt92tHChq/p6coIKKvKyP4723PF
 R2L03iO8jMfsX+HwL2ivblSZ/lFExEgalWET56aogZClRQVynC0NMOnDEdluYGaT
 XJZPib9sRqQOF36+G9Bcy4zlqjj1LoHwqpiCdAhtj3AACTKdoLjDK0sJ3Wn5E8lJ
 QfIb+oqOmOGNHN/fdSsxsNM1ptOqNb/sW2Gk4O+X9tYzG17m16oZEVkrv4FNhmeC
 mePl/7aX+aMoHkEYxvt9tF3kRDFbndcuHdNFtRxq0Tx9jELiR91ySjjs9bUr2Vnl
 kkihtfIMZngQjBgHe2PNlcF2t7gSIgSBVEvwxslcUlx3XvVEDP16RKJV52aL80uu
 ev4k0h72CTxI1lZuNuW4cJYDKF/wJPqPtQ8+GQfOZxG7yuM8tOc=
 =3UGk
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.8 kernel cycle.

  It's just really boring this time. Zero core changes. Just linear
  development, cleanups and misc noncritical fixes. Some new drivers for
  very new Qualcomm and Intel chips.

  New drivers:

   - Intel Jasper Lake support.

   - NXP Freescale i.MX8DXL support.

   - Qualcomm SM8250 support.

   - Renesas R8A7742 SH-PFC support.

  Driver improvements:

   - Severe cleanup and modernization of the MCP23s08 driver.

   - Mediatek driver modularized.

   - Setting config supported in the Meson driver.

   - Wakeup support for the Broadcom BCM7211"

* tag 'pinctrl-v5.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (72 commits)
  pinctrl: sprd: Fix the incorrect pull-up definition
  pinctrl: pxa: pxa2xx: Remove 'pxa2xx_pinctrl_exit()' which is unused and broken
  pinctrl: freescale: imx: Use 'devm_of_iomap()' to avoid a resource leak in case of error in 'imx_pinctrl_probe()'
  pinctrl: freescale: imx: Fix an error handling path in 'imx_pinctrl_probe()'
  pinctrl: sirf: add missing put_device() call in sirfsoc_gpio_probe()
  pinctrl: imxl: Fix an error handling path in 'imx1_pinctrl_core_probe()'
  pinctrl: bcm2835: Add support for wake-up interrupts
  pinctrl: bcm2835: Match BCM7211 compatible string
  dt-bindings: pinctrl: Document optional BCM7211 wake-up interrupts
  dt-bindings: pinctrl: Document 7211 compatible for brcm, bcm2835-gpio.txt
  dt-bindings: pinctrl: stm32: Add missing interrupts property
  pinctrl: at91-pio4: Add COMPILE_TEST support
  pinctrl: Fix return value about devm_platform_ioremap_resource()
  MAINTAINERS: Renesas Pin Controllers are supported
  dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support
  pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2
  pinctrl: ocelot: Remove instance number from pin functions
  pinctrl: ocelot: Always register GPIO driver
  dt-bindings: pinctrl: rockchip: update example
  pinctrl: amd: Add ACPI dependency
  ...
2020-06-07 16:13:43 -07:00
Linus Torvalds
9aa900c809 Char/Misc driver patches for 5.8-rc1
Here is the large set of char/misc driver patches for 5.8-rc1
 
 Included in here are:
 	- habanalabs driver updates, loads
 	- mhi bus driver updates
 	- extcon driver updates
 	- clk driver updates (approved by the clock maintainer)
 	- firmware driver updates
 	- fpga driver updates
 	- gnss driver updates
 	- coresight driver updates
 	- interconnect driver updates
 	- parport driver updates (it's still alive!)
 	- nvmem driver updates
 	- soundwire driver updates
 	- visorbus driver updates
 	- w1 driver updates
 	- various misc driver updates
 
 In short, loads of different driver subsystem updates along with the
 drivers as well.
 
 All have been in linux-next for a while with no reported issues.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXtzkHw8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+yldOwCgus/DgpnI1UL4z+NdBxJrAXtkPmgAn2sgTUea
 i5RblCmcVMqvHaGtYkY+
 =tScN
 -----END PGP SIGNATURE-----

Merge tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver updates from Greg KH:
 "Here is the large set of char/misc driver patches for 5.8-rc1

  Included in here are:

   - habanalabs driver updates, loads

   - mhi bus driver updates

   - extcon driver updates

   - clk driver updates (approved by the clock maintainer)

   - firmware driver updates

   - fpga driver updates

   - gnss driver updates

   - coresight driver updates

   - interconnect driver updates

   - parport driver updates (it's still alive!)

   - nvmem driver updates

   - soundwire driver updates

   - visorbus driver updates

   - w1 driver updates

   - various misc driver updates

  In short, loads of different driver subsystem updates along with the
  drivers as well.

  All have been in linux-next for a while with no reported issues"

* tag 'char-misc-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (233 commits)
  habanalabs: correctly cast u64 to void*
  habanalabs: initialize variable to default value
  extcon: arizona: Fix runtime PM imbalance on error
  extcon: max14577: Add proper dt-compatible strings
  extcon: adc-jack: Fix an error handling path in 'adc_jack_probe()'
  extcon: remove redundant assignment to variable idx
  w1: omap-hdq: print dev_err if irq flags are not cleared
  w1: omap-hdq: fix interrupt handling which did show spurious timeouts
  w1: omap-hdq: fix return value to be -1 if there is a timeout
  w1: omap-hdq: cleanup to add missing newline for some dev_dbg
  /dev/mem: Revoke mappings when a driver claims the region
  misc: xilinx-sdfec: convert get_user_pages() --> pin_user_pages()
  misc: xilinx-sdfec: cleanup return value in xsdfec_table_write()
  misc: xilinx-sdfec: improve get_user_pages_fast() error handling
  nvmem: qfprom: remove incorrect write support
  habanalabs: handle MMU cache invalidation timeout
  habanalabs: don't allow hard reset with open processes
  habanalabs: GAUDI does not support soft-reset
  habanalabs: add print for soft reset due to event
  habanalabs: improve MMU cache invalidation code
  ...
2020-06-07 10:59:32 -07:00
Linus Torvalds
e611c0fe31 USB/PHY driver updates for 5.8-rc1
Here are the large set of USB and PHY driver updates for 5.8-rc1.
 
 Nothing huge, just lots of little things:
 	- USB gadget fixes and additions all over the place
 	- new PHY drivers
 	- PHY driver fixes and updates
 	- XHCI driver updates
 	- musb driver updates
 	- more USB-serial driver ids added
 	- various USB quirks added
 	- thunderbolt minor updates and fixes
 	- typec updates and additions
 
 Full details are in the shortlog.
 
 All of these have been in linux-next for a while with no reported
 issues.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQT0tgzFv3jCIUoxPcsxR9QN2y37KQUCXtzqVA8cZ3JlZ0Brcm9h
 aC5jb20ACgkQMUfUDdst+ynftwCfeanyI6TR5AdfJVZN50B6/ySvVwcAn07i9VRX
 tnt2kz0UqReYpLt0wyJ7
 =YP7o
 -----END PGP SIGNATURE-----

Merge tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Pull USB/PHY driver updates from Greg KH:
 "Here are the large set of USB and PHY driver updates for 5.8-rc1.

  Nothing huge, just lots of little things:

   - USB gadget fixes and additions all over the place

   - new PHY drivers

   - PHY driver fixes and updates

   - XHCI driver updates

   - musb driver updates

   - more USB-serial driver ids added

   - various USB quirks added

   - thunderbolt minor updates and fixes

   - typec updates and additions

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'usb-5.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (245 commits)
  usb: dwc3: meson-g12a: fix USB2 PHY initialization on G12A and A1 SoCs
  usb: dwc3: meson-g12a: fix error path when fetching the reset line fails
  Revert "dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings"
  Revert "dt-bindings: usb: qcom,dwc3: Add compatible for SC7180"
  Revert "dt-bindings: usb: qcom,dwc3: Introduce interconnect properties for Qualcomm DWC3 driver"
  USB: serial: ch341: fix lockup of devices with limited prescaler
  USB: serial: ch341: add basis for quirk detection
  CDC-ACM: heed quirk also in error handling
  USB: serial: option: add Telit LE910C1-EUX compositions
  usb: musb: Fix runtime PM imbalance on error
  usb: musb: jz4740: Prevent lockup when CONFIG_SMP is set
  usb: musb: mediatek: add reset FADDR to zero in reset interrupt handle
  usb: musb: use true for 'use_dma'
  usb: musb: start session in resume for host port
  usb: musb: return -ESHUTDOWN in urb when three-strikes error happened
  USB: serial: qcserial: add DW5816e QDL support
  thunderbolt: Add trivial .shutdown
  usb: dwc3: keystone: Turn on USB3 PHY before controller
  dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property
  dt-bindings: usb: convert keystone-usb.txt to YAML
  ...
2020-06-07 09:42:16 -07:00
Linus Torvalds
9d71d3cd9e ARM: DT changes for v5.8
This is the set of device tree changes, mostly covering new
 hardware support, with 577 patches touching a little over 500
 files.
 
 There are five new Arm SoCs supported in this release, all of
 them for existing SoC families:
 
  - Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in
    both NAS devices and Android Set-top-box designs, along
    with the "Horseradish", "Lion Skin" and "Mjolnir" reference
    platforms; the Mele X1000 and Xnano X5 set-top-boxes and
    the Banana Pi BPi-M4 single-board computer.
 
  - Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC
    and the iW-RainboW-G21D-Qseven-RZG1H board/SoM
 
  - Rockchips RK3326 -- low-end 64-bit SoC along with the
    Odroid-GO Advance game console
 
 Newly added machines on already supported SoCs are:
 
  - AMLogic S905D based Smartlabs SML-5442TW TV box
 
  - AMLogic S905X3 based ODROID-C4 SBC
 
  - AMLogic S922XH based Beelink GT-King Pro TV box
 
  - Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC
 
  - Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2"
    and YADRO OpenPower P9 "Nicole"
 
  - Marvell Kirkwood based Check Point L-50 router
 
  - Mediatek MT8173 based Elm/Hana Chromebook laptops
 
  - Microchip SAMA5D2 "Industrial Connectivity Platform"
    reference board
 
  - NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit
 
  - Octavo OSDMP15x based Linux Automation MC-1 development board
 
  - Qualcomm SDM630 based Xiaomi Redmi Note 7 phone
 
  - Realtek RTD1295 based Xnano X5 TV Box
 
  - STMicroelectronics STM32MP1 based Stinger96 single-board
    computer and IoT Box
 
  - Samsung Exynos4210 based based Samsung Galaxy S2 phone
 
  - Socionext Uniphier based Akebi96 SBC
 
  - TI Keystone based K2G Evaluation board
 
  - TI am5729 based Beaglebone-AI development board
 
 Include device descriptions for additional hardware support in existing
 SoCs and machines based on all major SoC platforms:
 
  - AMlogic Meson
 
  - Allwinner sunxi
 
  - Arm Juno/VFP/Vexpress/Integrator
 
  - Broadcom bcm283x/bcm2711
 
  - Hisilicon hi6220
 
  - Marvell EBU
 
  - Mediatek MT27xx, MT76xx, MT81xx and MT67xx
 
  - Microchip SAMA5D2
 
  - NXP i.MX6/i.MX7/i.MX8 and Layerscape
 
  - Nvidia Tegra
 
  - Qualcomm Snapdragon
 
  - Renesas r8a77961, r8a7791
 
  - Rockchips RK32xx/RK33xx
 
  - ST-Ericsson ux500
 
  - STMicroelectronics SMT32
 
  - Samsung Exynos and S5PV210
 
  - Socionext Uniphier
 
  - TI OMAP5/DRA7 and Keystone
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAl7ZWskACgkQmmx57+YA
 GNl60xAAtW8fmOerc1JvUSNZFN6PApVexhNUDPnc0Wytzsi67v9KKTz7CNxEaO6z
 o466PfCObhi8IlLa1NmJxhSRXjv84JnbUODkiLeWhpX3HWE4rWhVz+/+gukmIah4
 H8Q3ehLyatgsGopXwBWShKoQmls2H4v9ETxKwx60Yj/HKqZeay7SLmLXbZ0SvFmZ
 5kkROmXiFg5iWjtALuibJWCsG1o5Hsfl8JMiPsr3W+O2hTmm4AvJ3ESkCFeqqJ1M
 ccxTEaFhakM/U6xujQYG/mSbRox6mnxZukYzQLh+K0ccP7yvS5J90GOE3B7hNDFy
 qZiB6hfrX6Rmcr7k0nhAzTDOOfHF+DmikGTKh9BvpOenklhHu9AYQlZwh5gK3Svw
 G5T3mAKMd3YF4ywJHNUKtzVPp/Q786CXq08PdAY+tDiLo02UIR5WjOQ9at2JJKDG
 bfUQClyii+EtOqgOTmIPH2yUsYgVsbbv4F7SPk/c4BEn5od9a+bLoIne7yu8sy6M
 IdW8klUtoswzmH9lGlOjUic4pMrRVY+8gSgtETSF0sePoapcQUJg6gEEygvj4H36
 BWFVHJK0WGQ2PWb3HHqRa20PJ92Jn65p1uK0eox4qkxd24KgpV6l2aAfx7FMUw47
 vqxb59ogFsC+XIZ5OSG0fYfejnwgfTSJLodrJrk9UdvXb6nwo/Q=
 =17kt
 -----END PGP SIGNATURE-----

Merge tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM devicetree updates from Arnd Bergmann:
 "This is the set of device tree changes, mostly covering new hardware
  support, with 577 patches touching a little over 500 files.

  There are five new Arm SoCs supported in this release, all of them for
  existing SoC families:

   - Realtek RTD1195, RTD1395 and RTD1619 -- three SoCs used in both NAS
     devices and Android Set-top-box designs, along with the
     "Horseradish", "Lion Skin" and "Mjolnir" reference platforms; the
     Mele X1000 and Xnano X5 set-top-boxes and the Banana Pi BPi-M4
     single-board computer.

   - Renesas RZ/G1H (r8a7742) -- a high-end 32-bit industrial SoC and
     the iW-RainboW-G21D-Qseven-RZG1H board/SoM

   - Rockchips RK3326 -- low-end 64-bit SoC along with the Odroid-GO
     Advance game console

  Newly added machines on already supported SoCs are:

   - AMLogic S905D based Smartlabs SML-5442TW TV box

   - AMLogic S905X3 based ODROID-C4 SBC

   - AMLogic S922XH based Beelink GT-King Pro TV box

   - Allwinner A20 based Olimex A20-OLinuXino-LIME-eMMC SBC

   - Aspeed ast2500 based BMCs in Facebook x86 "Yosemite V2" and YADRO
     OpenPower P9 "Nicole"

   - Marvell Kirkwood based Check Point L-50 router

   - Mediatek MT8173 based Elm/Hana Chromebook laptops

   - Microchip SAMA5D2 "Industrial Connectivity Platform" reference
     board

   - NXP i.MX8m based Beacon i.MX8m-Mini SoM development kit

   - Octavo OSDMP15x based Linux Automation MC-1 development board

   - Qualcomm SDM630 based Xiaomi Redmi Note 7 phone

   - Realtek RTD1295 based Xnano X5 TV Box

   - STMicroelectronics STM32MP1 based Stinger96 single-board computer
     and IoT Box

   - Samsung Exynos4210 based based Samsung Galaxy S2 phone

   - Socionext Uniphier based Akebi96 SBC

   - TI Keystone based K2G Evaluation board

   - TI am5729 based Beaglebone-AI development board

  Include device descriptions for additional hardware support in
  existing SoCs and machines based on all major SoC platforms:

   - AMlogic Meson

   - Allwinner sunxi

   - Arm Juno/VFP/Vexpress/Integrator

   - Broadcom bcm283x/bcm2711

   - Hisilicon hi6220

   - Marvell EBU

   - Mediatek MT27xx, MT76xx, MT81xx and MT67xx

   - Microchip SAMA5D2

   - NXP i.MX6/i.MX7/i.MX8 and Layerscape

   - Nvidia Tegra

   - Qualcomm Snapdragon

   - Renesas r8a77961, r8a7791

   - Rockchips RK32xx/RK33xx

   - ST-Ericsson ux500

   - STMicroelectronics SMT32

   - Samsung Exynos and S5PV210

   - Socionext Uniphier

   - TI OMAP5/DRA7 and Keystone"

* tag 'arm-dt-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (564 commits)
  ARM: dts: keystone: Rename "msmram" node to "sram"
  arm: dts: mt2712: add uart APDMA to device tree
  arm64: dts: mt8183: add mmc node
  arm64: dts: mt2712: add ethernet device node
  arm64: tegra: Make the RTC a wakeup source on Jetson Nano and TX1
  ARM: dts: mmp3: Add the fifth SD HCI
  ARM: dts: berlin*: Fix up the SDHCI node names
  ARM: dts: mmp3: Fix USB & USB PHY node names
  ARM: dts: mmp3: Fix L2 cache controller node name
  ARM: dts: mmp*: Fix up encoding of the /rtc interrupts property
  ARM: dts: pxa*: Fix up encoding of the /rtc interrupts property
  ARM: dts: pxa910: Fix the gpio interrupt cell number
  ARM: dts: pxa3xx: Fix up encoding of the /gpio interrupts property
  ARM: dts: pxa168: Fix the gpio interrupt cell number
  ARM: dts: pxa168: Add missing address/size cells to i2c nodes
  ARM: dts: dove: Fix interrupt controller node name
  ARM: dts: kirkwood: Fix interrupt controller node name
  arm64: dts: Add SC9863A emmc and sd card nodes
  arm64: dts: Add SC9863A clock nodes
  arm64: dts: mt6358: add PMIC MT6358 related nodes
  ...
2020-06-04 20:02:14 -07:00
Stephen Boyd
166e4b4841 Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into clk-next
- Support IDT VersaClock 5P49V5925
 - Bunch of updates for HSDK clock generation unit (CGU) driver
 - New clk driver for Baikal-T1 SoCs

* clk-vc5:
  dt: Add bindings for IDT VersaClock 5P49V5925
  clk: vc5: Add support for IDT VersaClock 5P49V6965

* clk-hsdk:
  CLK: HSDK: CGU: add support for 148.5MHz clock
  CLK: HSDK: CGU: support PLL bypassing
  CLK: HSDK: CGU: check if PLL is bypassed first

* clk-mediatek:
  clk: mediatek: assign the initial value to clk_init_data of mtk_mux
  clk: mediatek: Add MT6765 clock support
  clk: mediatek: add mt6765 clock IDs
  dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
  dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
  dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC

* clk-baikal:
  clk: Add Baikal-T1 CCU Dividers driver
  clk: Add Baikal-T1 CCU PLLs driver
  dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
  dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
2020-06-01 13:00:56 -07:00
Stephen Boyd
5debcd01e2 Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-silabs' into clk-next
- Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
 - Add support for X1830 and X1000 Ingenic SoC clk controllers
 - Add support for Qualcomm's MSM8939 Generic Clock Controller
 - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
 - Enable supply regulators for GPU gdscs on Qualcomm SoCs
 - Add support for Si5342, Si5344 and Si5345 chips

* clk-mmp:
  clk: mmp2: Add audio clock controller driver
  dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding
  clk: mmp2: Add support for power islands
  dt-bindings: marvell,mmp2: Add ids for the power domains
  dt-bindings: clock: Make marvell,mmp2-clock a power controller
  clk: mmp2: Add the audio clock
  clk: mmp2: Add the I2S clocks
  clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init()
  clk: mmp2: Move thermal register defines up a bit
  dt-bindings: marvell,mmp2: Add clock id for the Audio clock
  dt-bindings: marvell,mmp2: Add clock id for the I2S clocks
  clk: mmp: frac: Allow setting bits other than the numerator/denominator
  clk: mmp: frac: Do not lose last 4 digits of precision

* clk-intel:
  clk: intel: remove redundant initialization of variable rate64
  clk: intel: Add CGU clock driver for a new SoC
  dt-bindings: clk: intel: Add bindings document & header file for CGU

* clk-ingenic:
  clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused
  clk: X1000: Add FIXDIV for SSI clock of X1000.
  dt-bindings: clock: Add and reorder ABI for X1000.
  clk: Ingenic: Add CGU driver for X1830.
  dt-bindings: clock: Add X1830 clock bindings.
  clk: Ingenic: Adjust cgu code to make it compatible with X1830.
  clk: Ingenic: Remove unnecessary spinlock when reading registers.

* clk-qcom:
  clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
  dt-bindings: clock: Add YAML schemas for QCOM A53 PLL
  clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller
  clk: qcom: gcc: Add support for Secure control source clock
  dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
  clk: qcom: gcc: Add support for a new frequency for SC7180
  clk: qcom: Add DT bindings for MSM8939 GCC
  clk: qcom: gcc: Add missing UFS clocks for SM8150
  clk: qcom: gcc: Add GPU and NPU clocks for SM8150
  clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc
  clk: qcom: gdsc: Handle GDSC regulator supplies
  clk: qcom: msm8916: Fix the address location of pll->config_reg

* clk-silabs:
  clk: clk-si5341: Add support for the Si5345 series
2020-06-01 13:00:28 -07:00
Stephen Boyd
b6f3162d0e Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2600' into clk-next
* clk-unisoc:
  clk: sprd: add mipi_csi_xx gate clocks
  clk: sprd: add dt-bindings include for mipi_csi_xx clocks
  dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A
  clk: sprd: check its parent status before reading gate clock
  clk: sprd: return correct type of value for _sprd_pll_recalc_rate
  clk: sprd: mark the local clock symbols static

* clk-trivial:
  clk: versatile: remove redundant assignment to pointer clk
  clk: clk-xgene: Fix a typo in Kconfig
  clk: Remove unused inline function clk_debug_reparent

* clk-bcm:
  clk: bcm2835: Constify struct debugfs_reg32
  clk: bcm2835: Remove casting to bcm2835_clk_register
  clk: bcm2835: Fix return type of bcm2835_register_gate

* clk-st:
  clk: clk-flexgen: fix clock-critical handling

* clk-ast2600:
  clk: ast2600: Fix AHB clock divider for A1
2020-06-01 13:00:21 -07:00
Stephen Boyd
8c88e568b5 Merge branches 'clk-tegra', 'clk-imx', 'clk-zynq', 'clk-socfpga', 'clk-at91' and 'clk-ti' into clk-next
- Support custom flags in Xilinx zynq firmware
 - Various small fixes to the Xilinx clk driver
 - Support for Intel Agilex clks

* clk-tegra:
  clk: tegra: Add Tegra210 CSI TPG clock gate
  clk: tegra30: Use custom CCLK implementation
  clk: tegra20: Use custom CCLK implementation
  clk: tegra: cclk: Add helpers for handling PLLX rate changes
  clk: tegra: pll: Add pre/post rate-change hooks
  clk: tegra: Add custom CCLK implementation
  clk: tegra: Remove the old emc_mux clock for Tegra210
  clk: tegra: Implement Tegra210 EMC clock
  clk: tegra: Export functions for EMC clock scaling
  clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
  clk: tegra: Rename Tegra124 EMC clock source file
  dt-bindings: clock: tegra: Add clock ID for CSI TPG clock

* clk-imx:
  clk: imx: use imx8m_clk_hw_composite_bus for i.MX8M bus clk slice
  clk: imx: add imx8m_clk_hw_composite_bus
  clk: imx: add mux ops for i.MX8M composite clk
  clk: imx8m: migrate A53 clk root to use composite core
  clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
  clk: imx8mp: Define gates for pll1/2 fixed dividers
  clk: imx: imx8mp: fix pll mux bit
  clk: imx8m: drop clk_hw_set_parent for A53
  dt-bindings: clocks: imx8mp: Add ids for audiomix clocks
  clk: imx: Add helpers for passing the device as argument
  clk: imx: pll14xx: Add the device as argument when registering
  clk: imx: gate2: Allow single bit gating clock
  clk: imx: clk-pllv3: Use readl_relaxed_poll_timeout() for PLL lock wait
  clk: imx: clk-sscg-pll: Remove unnecessary blank lines
  clk: imx: drop the dependency on ARM64 for i.MX8M
  clk: imx7ulp: make it easy to change ARM core clk
  clk: imx: imx6ul: change flexcan clock to support CiA bitrates

* clk-zynq:
  clk: zynqmp: Make zynqmp_clk_get_max_divisor static
  clk: zynqmp: Update fraction clock check from custom type flags
  clk: zynqmp: Add support for custom type flags
  clk: zynqmp: fix memory leak in zynqmp_register_clocks
  clk: zynqmp: Fix invalid clock name queries
  clk: zynqmp: Fix divider2 calculation
  clk: zynqmp: Limit bestdiv with maxdiv

* clk-socfpga:
  clk: socfpga: agilex: add clock driver for the Agilex platform
  dt-bindings: documentation: add clock bindings information for Agilex
  clk: socfpga: add const to _ops data structures
  clk: socfpga: remove clk_ops enable/disable methods
  clk: socfpga: stratix10: use new parent data scheme

* clk-at91:
  clk: at91: allow setting all PMC clock parents via DT
  clk: at91: allow setting PCKx parent via DT
  clk: at91: optimize pmc data allocation
  clk: at91: pmc: decrement node's refcount
  clk: at91: pmc: do not continue if compatible not located
  clk: at91: Add peripheral clock for PTC

* clk-ti:
  clk: ti: dra7: remove two unused symbols
  clk: ti: dra7xx: fix RNG clock parent
  clk: ti: dra7xx: mark MCAN clock as DRA76x only
  clk: ti: dra7xx: fix gpu clkctrl parent
  clk: ti: omap5: Add proper parent clocks for l4-secure clocks
  clk: ti: omap4: Add proper parent clocks for l4-secure clocks
  clk: ti: composite: fix memory leak
2020-06-01 13:00:00 -07:00
Stephen Boyd
3a57530b7d Merge branches 'clk-selectable', 'clk-amlogic', 'clk-renesas', 'clk-samsung' and 'clk-allwinner' into clk-next
- Allow the COMMON_CLK config to be selectable

* clk-selectable:
  clk: Move HAVE_CLK config out of architecture layer
  MIPS: Loongson64: Drop asm/clock.h include
  ARM: mmp: Remove legacy clk code
  clk: Allow the common clk framework to be selectable
  mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OF
  MIPS: Remove redundant CLKDEV_LOOKUP selects
  h8300: Remove redundant CLKDEV_LOOKUP selects
  arm64: tegra: Remove redundant CLKDEV_LOOKUP selects
  ARM: Remove redundant CLKDEV_LOOKUP selects
  ARM: Remove redundant COMMON_CLK selects

* clk-amlogic:
  clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers
  clk: meson: meson8b: Make the CCF use the glitch-free VPU mux
  clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits
  clk: meson: meson8b: Fix the polarity of the RESET_N lines
  clk: meson: meson8b: Fix the first parent of vid_pll_in_sel
  clk: meson: g12a: Prepare the GPU clock tree to change at runtime
  clk: meson: gxbb: Prepare the GPU clock tree to change at runtime
  clk: meson: meson8b: make the hdmi_sys clock tree mutable
  clk: meson8b: export the HDMI system clock

* clk-renesas:
  dt-bindings: clock: renesas: mstp: Convert to json-schema
  dt-bindings: clock: renesas: div6: Convert to json-schema
  clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
  clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects
  clk: renesas: cpg-mssr: Add R8A7742 support
  dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding
  clk: renesas: Add r8a7742 CPG Core Clock Definitions
  dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros
  MAINTAINERS: Add DT Bindings for Renesas Clock Generators
  clk: renesas: r9a06g032: Fix some typo in comments
  dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support

* clk-samsung:
  clk: samsung: exynos5433: Add IGNORE_UNUSED flag to sclk_i2s1
  ARM/SAMSUNG EXYNOS ARM ARCHITECTURES: Use fallthrough;
  clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542x
  clk: samsung: Mark top ISP and CAM clocks on Exynos542x as critical

* clk-allwinner:
  clk: sunxi: Fix incorrect usage of round_down()
2020-06-01 12:59:46 -07:00
Manivannan Sadhasivam
a01822e94e dt-bindings: mailbox: Add devicetree binding for Qcom IPCC
Add devicetree YAML binding for Qualcomm Inter-Processor Communication
Controller (IPCC) block.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2020-05-30 18:10:27 -05:00
Serge Semin
11ea09b9e2 dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
After being gained by the CCU PLLs the signals must be transformed to
be suitable for the clock-consumers. This is done by a set of dividers
embedded into the CCU. A first block of dividers is used to create
reference clocks for AXI-bus of high-speed peripheral IP-cores of the
chip. The second block dividers alter the PLLs output signals to be then
consumed by SoC peripheral devices. Both block DT nodes are ordinary
clock-providers with standard set of properties supported. But in addition
to that each clock provider can be used to reset the corresponding clock
domain. This makes the AXI-bus and System Devices CCU DT nodes to be also
reset-providers.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
Link: https://lore.kernel.org/r/20200526222056.18072-3-Sergey.Semin@baikalelectronics.ru
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-30 11:04:35 -07:00
Serge Semin
aec6adc560 dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
Baikal-T1 Clocks Control Unit is responsible for transformation of a
signal coming from an external oscillator into clocks of various
frequencies to propagate them then to the corresponding clocks
consumers (either individual IP-blocks or clock domains). In order
to create a set of high-frequency clocks the external signal is
firstly handled by the embedded into CCU PLLs. So the corresponding
dts-node is just a normal clock-provider node with standard set of
properties. Note as being part of the Baikal-T1 System Controller its
DT node is supposed to be a child the system controller node.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
Link: https://lore.kernel.org/r/20200526222056.18072-2-Sergey.Semin@baikalelectronics.ru
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-30 11:04:34 -07:00
Mars Cheng
eb7beb65ac clk: mediatek: add mt6765 clock IDs
Add MT6765 clock dt-bindings, include topckgen, apmixedsys,
infracfg, mcucfg and subsystem clocks.

Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1582278742-1626-5-git-send-email-macpaul.lin@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 21:23:04 -07:00
Jeffrey Hugo
b1e8d713e6 clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src
ufs_unipro_core_clk_src is required to allow UFS to clock scale for power
savings.

Fixes: b5f5f525c5 ("clk: qcom: Add MSM8998 Global Clock Control (GCC) driver")
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lkml.kernel.org/r/20200528142205.44003-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 16:52:25 -07:00
周琰杰 (Zhou Yanjie)
424c85e1ff dt-bindings: clock: Add and reorder ABI for X1000.
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
  directly derived from the output of SSIPLL, but from the clock
  obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
  is added for this purpose, it must between "X1000_CLK_SSIPLL"
  and "X1000_CLK_SSIMUX", otherwise an error will occurs when
  initializing the clock. These ABIs are only used for X1000, and
  I'm sure that no other devicetree out there is using these ABIs,
  so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200528031549.13846-7-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 16:13:19 -07:00
周琰杰 (Zhou Yanjie)
9a618e6f8c dt-bindings: clock: Add X1830 clock bindings.
Add the clock bindings for the X1830 Soc from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200528031549.13846-5-zhouyanjie@wanyeetech.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-28 16:13:19 -07:00
Lubomir Rintel
e787c5b725 dt-bindings: clock: Add Marvell MMP Audio Clock Controller binding
This describes the bindings for a controller that generates master and bit
clocks for the I2S interface.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-13-lkundrak@v3.sk
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 17:55:12 -07:00
Lubomir Rintel
17d43046fd dt-bindings: marvell,mmp2: Add ids for the power domains
On MMP2 the audio and GPU blocks are on separate power islands. On MMP3
the camera block's power is also controlled separately.

Add the numbers that we could use to refer to the power domains for
respective power islands from the device tree.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200519224151.2074597-11-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 17:55:12 -07:00
Lubomir Rintel
c227df7a09 dt-bindings: marvell,mmp2: Add clock id for the Audio clock
This clocks the Audio block.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200519224151.2074597-5-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 17:55:11 -07:00
Lubomir Rintel
edcec4a869 dt-bindings: marvell,mmp2: Add clock id for the I2S clocks
There are two of these on a MMP2.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200519224151.2074597-4-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-27 17:55:11 -07:00
Chunyan Zhang
d7160288f9 clk: sprd: add dt-bindings include for mipi_csi_xx clocks
mipi_csi_xx clocks are used by camera sensors.

Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200527053638.31439-4-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 23:41:14 -07:00
Michał Mirosław
03a1ee1dad clk: at91: allow setting all PMC clock parents via DT
We need to have clocks accessible via phandle to select them
as peripheral clock parent using assigned-clock-parents in DT.
Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.pl
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 20:22:50 -07:00
Michał Mirosław
99767cd440 clk: at91: allow setting PCKx parent via DT
This exposes PROGx clocks for use in assigned-clocks DeviceTree property
for selecting PCKx parent clock.

Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Link: https://lkml.kernel.org/r/0054532c00163ddf405dad658b32f0d7d97fcc8e.1588630999.git.mirq-linux@rere.qmqm.pl
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 20:22:43 -07:00
Taniya Das
3005b17c5e dt-bindings: clock: Add gcc_sec_ctrl_clk_src clock ID
The gcc_sec_ctrl_clk_src clock is required to be controlled by the
secure controller driver.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1589709861-27580-3-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 19:22:05 -07:00
Dinh Nguyen
6b3c59780e dt-bindings: documentation: add clock bindings information for Agilex
Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20200512181647.5071-4-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 19:13:05 -07:00
Rahul Tanwar
e2266f4c38 dt-bindings: clk: intel: Add bindings document & header file for CGU
Clock generation unit(CGU) is a clock controller IP of Intel's Lightning
Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock
controller driver of LGM.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
Link: https://lkml.kernel.org/r/8dce2be13195aab20c6b11fca6af0fffe22d5241.1587102634.git.rahul.tanwar@linux.intel.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-26 18:47:20 -07:00
Arnd Bergmann
34a07a8da3 arm64: dts: Amlogic updates for v5.8
Highlights:
 - new boards :Beelink GT-King Pro (G12B SoC), Smartlabs SML-5442TW
   (S905D), Hardkernel ODROID-C4 (SM1)
 - audio: support for GX-family SoCs
 - audio: internal DAC support
 - use the new USB control driver for GXL and GXM
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl7G0fMACgkQWTcYmtP7
 xmXYOg/8Dp9b4OpTxZ8GQmD6sUrPFxnWi9mckDGYAqvtzNA2MdTzrkJAo6D9jQqC
 83uqqVGUKmgSuDnUKfesLLUHPu464Ab2cWLsuKsMIJNO+B9sYX0SAzePT53mdKDR
 WDCS9h0UN+smL3WjEb/dZ3gthiXYaBhSEtMyTLq47MJTcbCwvVsvOJmdM2pXkzRx
 3kosB22+vLVWyih2tSSIdfzqn3nNFRh1Cs0pnqynMjfkTIsr5XTgmN+BFKmFVefA
 qHPpgJ1fGwRBS6sQg/1h3H1zC6pUAXCYXOhaBeOzOumVp3jxR3E0aqux8/CwqEWX
 ppkU6sCpuI/BZcHK+76+87SUyBOuuZ9TK2SQuoNGEzT0sZ8GZHTfRD/Edw5YYtGe
 l9RpJyq11QOPEv+/q5nNMD9mLzd2pH5WItiO6inj0V03g2jS5t2Kz05awolDbESZ
 ELPq5iKHttdxvcV1e5HK5HwKevkXW2+EJSaBRTzFneheQllryZubPVCfV02Ybijf
 k97WLs2swKpRjvsIdg2o6MXy8xd/kmj5zclgj6z2S9FF+rgTl9jw3l/GIDZ2kgEx
 0YXQL9Pec8xtdux//WwIP931TIHUnI5IUTjGOWy1Ch/QLwA/BxVy+BeQVCAidN3Y
 5U6NbowE5UdozThi1BMxVokPWoF9XJlpcQISrmuVrgRtnbfiaMY=
 =JbXj
 -----END PGP SIGNATURE-----

Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.8

Highlights:
- new boards :Beelink GT-King Pro (G12B SoC), Smartlabs SML-5442TW
  (S905D), Hardkernel ODROID-C4 (SM1)
- audio: support for GX-family SoCs
- audio: internal DAC support
- use the new USB control driver for GXL and GXM

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (33 commits)
  arm64: dts: meson-g12b-gtking-pro: add initial device-tree
  dt-bindings: arm: amlogic: add support for the Beelink GT-King Pro
  arm64: dts: meson-g12b-gtking: add initial device-tree
  dt-bindings: arm: amlogic: add support for the Beelink GT-King
  arm64: dts: meson: convert ugoos-am6 to common w400 dtsi
  arm64: dts: meson: add ethernet interrupt to wetek dtsi
  arm64: dts: meson: add support for the Smartlabs SML-5442TW
  dt-bindings: arm: amlogic: add support for the Smartlabs SML-5442TW
  dt-bindings: add vendor prefix for Smartlabs LLC
  arm64: dts: meson: g12: add internal DAC glue
  arm64: dts: meson: g12: add internal DAC
  arm64: dts: meson: libretech-pc: add internal DAC support
  arm64: dts: meson: libretech-ac: add internal DAC support
  arm64: dts: meson: libretech-cc: add internal DAC support
  arm64: dts: meson: p230-q200: add internal DAC support
  arm64: dts: meson: gxl: add acodec support
  arm64: dts: meson-sm1: add support for Hardkernel ODROID-C4
  dt-bindings: arm: amlogic: add odroid-c4 bindings
  arm64: dts: meson-sm1: add cpu thermal nodes
  arm64: dts: meson-g12b: move G12B thermal nodes to meson-g12b.dtsi
  ...

Link: https://lore.kernel.org/r/5ec6f56a.1c69fb81.fc5d5.9ca6@mx.google.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-26 00:20:16 +02:00
Arnd Bergmann
7b972f3830 i.MX drivers update for 5.8:
- Optimize imx-scu driver to use one TX and one RX instead of four for
   talking to SCU.
 - Fix one possible message header corruption where the response is
   longer than the request.
 - Move System Control defines into dt-bindings header, so that DT can
   use them as well.
 - A couple of small fixups.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl7IeuUUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM5CpAf/VV2krqXlgTXA1Ppl+ivdGkx9ntwo
 dVtZYNr65Z1iqp6yujW7cH/qulXfkaFanwDptq9ulBkG6uiyV06GCtBxpp3VhNOB
 60uaS8RsieYmCz3e8j4kZkMCBthpD72wt0DxF1TlJu2d/cWfsM4/bMbrx0qYiT0V
 J5FqcGH0xbe+E5YITdoPQbNxEig49q2P6BhkNLQelVQtVgM0lwSpDX3WRpCizch4
 bbKSVYudV/rGGPM7ZYM53N+ngwKZurRbIf7br1QgA4ZlQxdCtADB6IRd2RsfrC8P
 4BizRONfh46ogrnb9/P951RZu9H7VFRkTurnXdU+NcFK8HPYDGQmm7P2SQ==
 =cJwM
 -----END PGP SIGNATURE-----

Merge tag 'imx-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers

i.MX drivers update for 5.8:

- Optimize imx-scu driver to use one TX and one RX instead of four for
  talking to SCU.
- Fix one possible message header corruption where the response is
  longer than the request.
- Move System Control defines into dt-bindings header, so that DT can
  use them as well.
- A couple of small fixups.

* tag 'imx-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  firmware: imx: scu: Fix possible memory leak in imx_scu_probe()
  dt-bindings: firmware: imx: Add more system controls and PM clock types
  dt-bindings: firmware: imx: Move system control into dt-binding headfile
  firmware: imx: scu: Fix corruption of header
  firmware: imx-scu: Support one TX and one RX
  soc: imx8m: No need to put node when of_find_compatible_node() failed

Link: https://lore.kernel.org/r/20200523032516.11016-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-26 00:00:47 +02:00
Arnd Bergmann
9ffc30a66d media: tegra: Changes for v5.8-rc1
This contains a V4L2 video capture driver for Tegra210.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl6+pDETHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoZfLEACBVTUrkg3OwO9D/01Llr/DpAzMZpa7
 bjb462A+2ftgn41sw9Wg9hkdMpPYp3i1OSXgboPU9VxdZ3qVOEYiNp/uOMGWE1J3
 QOF720wSRgeGPf/+MJvicc0XHGv9Lz0LKjmI0wyfWKYIwyVWm4/UzxJ+JdM9FA2g
 ivuw5aA5XcxDt6lf++B/ZD3l1imXs7F8viPYW5O/ViNG5tQ0sLFb/PA4jlO05Fsk
 qm+1e0ga6Cz/MO7fDNQzJ0+EX0jFYABiQzrKx4hbMZVIlxm3H56U03dwb+dLcD37
 JLtAHMt6eEHX1hFYALG0lc9RY+8qOznt2bgbjcu8Fu5rgDqY+hLjRbDcgEEhw3y8
 wPXROJD+c6+9TNXOfRxG8PPn1dHccPEnU4AgbkpZtZrns+rGRp+5/kgw/7xIyzfq
 /T3euUPDGdQq9OkJlx6P5KVY9OkJgVmI6qP1/nBPqMSqmzLAyDlBIlCahRtCBEX/
 pWq1xlwccVKpRMIuBAXmNZre0W70+9/QqY41d+TbcVo4JfDbfJ/BUci9VFuCNGM1
 9jiFfs5OOOfVhtmJjnUcaDHKAe1Ie9aplEdbNQNkF/oVpEbEzPjtroon5tg9bmj5
 O5VhzBSamHvz4PU9HbtRtBhIdIOmmp/qd2I8gGc1LChtl9eY4pD4CkDwcxP/nMO6
 G2DLtELY+mJQ2Q==
 =ZA0j
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers

media: tegra: Changes for v5.8-rc1

This contains a V4L2 video capture driver for Tegra210.

* tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  media: tegra-video: Do not enable COMPILE_TEST
  MAINTAINERS: correct path in TEGRA VIDEO DRIVER
  media: tegra-video: Make tegra210_video_formats static
  MAINTAINERS: Add Tegra Video driver section
  media: tegra-video: Add Tegra210 Video input driver
  dt-bindings: i2c: tegra: Document Tegra210 VI I2C
  dt-bindings: tegra: Add VI and CSI bindings
  dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
  dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
  dt-bindings: clock: tegra: Remove PMC clock IDs
  dt-bindings: clock: tegra: Add clock ID for CSI TPG clock

Link: https://lore.kernel.org/r/20200515145311.1580134-7-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-25 23:28:35 +02:00
Arnd Bergmann
502afe7f04 Qualcomm driver updates for v5.8
This contains a large set of cleanups, bug fixes, general improvements
 and documentation fixes for the RPMH driver. It adds a debugfs mechanism
 for inspecting Command DB. Socinfo got the "soc_id" attribute defines
 and definitions for a various variants of MSM8939.
 
 RPMH, RPMPD and RPMHPD where made possible to build as modules, but RPMH
 had to be reverted due to a compilation issue when tracing is enabled.
 
 RPMHPD gained power-domains for the SM8250 voltage corners.
 
 The SCM driver gained fixes for two build warnings and the SMP2P had an
 unnecessary error print removed.
 -----BEGIN PGP SIGNATURE-----
 
 iQJPBAABCAA5FiEEBd4DzF816k8JZtUlCx85Pw2ZrcUFAl7DZcEbHGJqb3JuLmFu
 ZGVyc3NvbkBsaW5hcm8ub3JnAAoJEAsfOT8Nma3FEwIQAK1TrENzsRjB23fY4pEW
 +hN/SkfMjNPsinmyNOHCo03MQzdFIKUl40aNvaHh3foQXaSG4TW12iot9Ul5nsxn
 /u6dCSzl15FK7pHYj/VQPWTz2WvpANVqsm6G5tf43hBg2TnStbK1AsxgJ6aq47fp
 QHehMbfeKpF/gltEowv1b+H7xwNFY7eqlQ9O9umYm3hUQh3Bl5mI6PdbkazDdO1j
 l/vHuQKkZXRdHtD1BxGBfvhPtM4NWDbOPeWWrw8HRFM5muDPgK9mXMRGDcv+fpHq
 4I3670xiTWK1Mfz9+FRBMoxLkIWT6zXILg9aNzuZMTOLoNRt3s6VNdne6uf3naND
 2Nrcu7t0b+4xWGbdwwpiAFZm8C6l+R1WTCiY4iOJXDychhVvyVwOLzPdZ4i8Pzx9
 a4UJDElu8xj2g++oCcjK816IdNwkA46bM7qVz4mkHRUBMkmK9AU7okBA9HQfbP64
 MrKPaUljyZuy7zonpJJBBDKLDEFa9a1pI8sehU8p+MUldxYB/4f/iGC3KzyDvv4Q
 Uzj6AqdP5pjgIxz98YgpOPPl8pwg1c5OgblNLWoHj4yTaqUzT0ZHIRyQO/O/+3Lg
 HwCrSy+f3+tgzts3DhyVRmOkOXFHfflSdf4rfKtbiq435yB2dz60dt77dJ0jQuBV
 M9MiF+SE9oASUupPhs47kNte
 =tkhb
 -----END PGP SIGNATURE-----

Merge tag 'qcom-drivers-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers

Qualcomm driver updates for v5.8

This contains a large set of cleanups, bug fixes, general improvements
and documentation fixes for the RPMH driver. It adds a debugfs mechanism
for inspecting Command DB. Socinfo got the "soc_id" attribute defines
and definitions for a various variants of MSM8939.

RPMH, RPMPD and RPMHPD where made possible to build as modules, but RPMH
had to be reverted due to a compilation issue when tracing is enabled.

RPMHPD gained power-domains for the SM8250 voltage corners.

The SCM driver gained fixes for two build warnings and the SMP2P had an
unnecessary error print removed.

* tag 'qcom-drivers-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (42 commits)
  Revert "soc: qcom: rpmh: Allow RPMH driver to be loaded as a module"
  soc: qcom: rpmh-rsc: Remove the pm_lock
  soc: qcom: rpmh-rsc: Simplify locking by eliminating the per-TCS lock
  kernel/cpu_pm: Fix uninitted local in cpu_pm
  soc: qcom: rpmh-rsc: We aren't notified of our own failure w/ NOTIFY_BAD
  soc: qcom: rpmh-rsc: Correctly ignore CPU_CLUSTER_PM notifications
  firmware: qcom_scm-legacy: Replace zero-length array with flexible-array
  soc: qcom: rpmh-rsc: Timeout after 1 second in write_tcs_reg_sync()
  soc: qcom: rpmh-rsc: Factor "tcs_reg_addr" and "tcs_cmd_addr" calculation
  soc: qcom: socinfo: add msm8936/39 and apq8036/39 soc ids
  soc: qcom: aoss: Add SM8250 compatible
  soc: qcom: pdr: Remove impossible error condition
  soc: qcom: rpmh: Dirt can only make you dirtier, not cleaner
  soc: qcom: rpmhpd: Add SM8250 power domains
  firmware: qcom_scm: fix bogous abuse of dma-direct internals
  dt-bindings: soc: qcom: apr: Use generic node names for APR services
  firmware: qcom_scm: Remove unneeded conversion to bool
  soc: qcom: cmd-db: Properly endian swap the slv_id for debugfs
  soc: qcom: cmd-db: Use 5 digits for printing address
  soc: qcom: cmd-db: Cast sizeof() to int to silence field width warning
  ...

Link: https://lore.kernel.org/r/20200519052533.1250024-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-25 23:19:06 +02:00
Arnd Bergmann
0417a5c6a4 Reset controller updates for v5.8
This tag adds support for i.MX8MP and i.MX8MN SoCs to the i.MX7 reset
 controller driver, extends the Hi6220 reset driver to support the AO
 reset controller used to bring the Mali450 GPU out of reset, and adds
 a define for the internal DAC reset line on Amlogic GXL SoCs.
 -----BEGIN PGP SIGNATURE-----
 
 iI4EABYIADYWIQRRO6F6WdpH1R0vGibVhaclGDdiwAUCXr6nvBgccGhpbGlwcC56
 YWJlbEBnbWFpbC5jb20ACgkQ1YWnJRg3YsB63QEA8Rig0c9jN9LBDxVmqxB8dU/k
 4fc3vMtuxbbrzmoD9rIA/ApMrQe77k/JW+hCSBrgCQWlvHInRncKwrEIhWk7ADkN
 =BaS5
 -----END PGP SIGNATURE-----

Merge tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux into arm/drivers

Reset controller updates for v5.8

This tag adds support for i.MX8MP and i.MX8MN SoCs to the i.MX7 reset
controller driver, extends the Hi6220 reset driver to support the AO
reset controller used to bring the Mali450 GPU out of reset, and adds
a define for the internal DAC reset line on Amlogic GXL SoCs.

* tag 'reset-for-v5.8' of git://git.pengutronix.de/pza/linux:
  reset: hi6220: Add support for AO reset controller
  reset: imx7: Add support for i.MX8MP SoC
  dt-bindings: reset: imx7: Document usage on i.MX8MP SoC
  dt-bindings: reset: imx7: Add support for i.MX8MN
  dt-bindings: reset: meson: add gxl internal dac reset

Link: https://lore.kernel.org/r/20200515143844.GA17201@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-25 17:01:34 +02:00
Arnd Bergmann
93f9fb1e4a soc: amlogic: driver updates for v5.8
- support GX SoCs in the EE power-controller driver
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEe4dGDhaSf6n1v/EMWTcYmtP7xmUFAl7Gz9cACgkQWTcYmtP7
 xmXc/A/+KjFrbfbLxzD3ECvsEEfWB9H9XrFUn1NDVU9MJipV9+sFKnnV3Px3C3VA
 ++J7nJ3uU6p5LzU09AaeqwciZgwP00/14SyijF9IifvzBntvzQAZ3ouexj1xSMVu
 eSU3Q12UeWwlUUT6kzdEwAjgQFdSZgX01fZGM6TiTY3SiHEw7R6wrKQPxzCaeSrw
 ElnKu9ukzqsI0oydpnaEWzXaSx/Rl27UUIV8iqWvIYk6dogCvF6svifmqaFEnDlO
 dn+Z4Y2m/I/yW94JMuajA3Iqt+vBcAge70GhcRZOUJqN0Pkg+gp4+vqieGHwcuGu
 Nqi3A95gthIJV0WY+1p8NkQ7EvougzD/zr6u5UQultL1y+hQNTmNh/kV0TJLnIo+
 kVIBfuCG1b5nvPIZ1dqGcS1u4OIWtU8vz5mYII+vAcGFucThdd5S3eVf3yDD5M+f
 vKlJ/M9dugkTfMi7iZSbmP6oTwFuRRqJ1OXpaxvdwtYBNd7pNDMel5elLRUxu0zZ
 jf83C8jgEHJyNspgTrBuWc7sRYnaSyMu79QNNTorSNI7WOPLer+YluBrZdxahp54
 OwjkiWDA/mX/Ty5wyRpRxWfdpCbcKAHx17uHuXxKOnuvJkwVdDqGdnNzX2IcYuxa
 0MGSdAZdwcapK1L11xAzK4PBHB15xJRI3Sf7MTRA9HGWHv6t12k=
 =nn2j
 -----END PGP SIGNATURE-----

Merge tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/drivers

soc: amlogic: driver updates for v5.8
- support GX SoCs in the EE power-controller driver

* tag 'amlogic-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  soc: amlogic: meson-ee-pwrc: add support for the Meson GX SoCs
  soc: amlogic: meson-ee-pwrc: add support for Meson8/Meson8b/Meson8m2
  dt-bindings: power: meson-ee-pwrc: add support for the Meson GX SoCs
  dt-bindings: power: meson-ee-pwrc: add support for Meson8/8b/8m2

Link: https://lore.kernel.org/r/5ec6f570.1c69fb81.a3753.711b@mx.google.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-25 16:58:09 +02:00
Arnd Bergmann
f0c59fd97c New soc variant the rk3326 which is essentially a px30 with only one
display controller and a new board using it, the Odroid Advance Go.
 sdcard regulator for the rockpro64 and a lot of devicetree fixes
 making the dt-binding check a lot happier.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl7F1N0QHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgV34CAChtYhGGRGEr8WwGL3WG1f8z1nwEfxEGaMx
 niLnchgR2kWRiPFV8SVHaNkcGj9+VkeA/F8mCrrKiPDPrsL+s5X6q2liAmEGnIWo
 OvlfyuIJNaSjnVxwhdZABIQsjjeLZI2i0OWGmq47vGopWaNWDGW9wrPlRslPrf4N
 AIww1TwjKYK8Et5ja3COwfSt1gn2/PwR09wTfQwCy7wi9At6UWOQsDmpyFbjuTgv
 GmPcQJZa2YtQovSM5FrbhguCKSGFSukopqqrrxmfsvlkz+xmZyeHN6MMpdNnwBXe
 Kf3VU2p6b+75YouuOcJAAueBj6b37/tvi7KK/MZszdG2pM85SL1z
 =BL2H
 -----END PGP SIGNATURE-----

Merge tag 'v5.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

New soc variant the rk3326 which is essentially a px30 with only one
display controller and a new board using it, the Odroid Advance Go.
sdcard regulator for the rockpro64 and a lot of devicetree fixes
making the dt-binding check a lot happier.

* tag 'v5.8-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (22 commits)
  arm64: dts: rockchip: fix pinctrl-names for gpio-leds node on rk3326-odroid-go2
  arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399
  arm64: dts: rockchip: add bus-width properties to mmc nodes for px30
  arm64: dts: rockchip: remove disable-wp from rk3308-roc-cc emmc node
  arm64: dts: rockchip: rename and label gpio-led subnodes
  arm64: dts: rockchip: fix defines in pd_vio node for rk3399
  arm64: dts: rockchip: fix &pinctrl phy sub nodename for rk3399-orangepi
  arm64: dts: rockchip: fix rtl8211e nodename for rk3399-orangepi
  arm64: dts: rockchip: fix &pinctrl phy sub nodename for rk3399-nanopi4
  arm64: dts: rockchip: fix rtl8211e nodename for rk3399-nanopi4
  arm64: dts: rockchip: fix rtl8211f nodename for rk3328 Beelink A1
  arm64: dts: rockchip: fix phy nodename for rk3328
  include: dt-bindings: rockchip: remove unused defines
  arm64: dts: rockchip: replace RK_FUNC defines in rk3326-odroid-go2
  arm64: dts: rockchip: Define the rockchip Video Decoder node on rk3399
  arm64: dts: rockchip: remove #sound-dai-cells from &spdif node of rk3399-hugsun-x99.dts
  arm64: dts: rockchip: remove #sound-dai-cells from &i2s1 node of rk3399-pinebook-pro.dts
  arm64: dts: rockchip: add Odroid Advance Go
  dt-bindings: Add binding for Hardkernel Odroid Go Advance
  arm64: dts: rockchip: add core devicetree for rk3326
  ...

Link: https://lore.kernel.org/r/1970481.V9vR1fIhX2@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21 23:14:11 +02:00
Arnd Bergmann
22c328b1bc dt-bindings: Changes for v5.8-rc1
This adds bindings for the CSI TPG clock on Tegra210, moves various
 clocks from the clock and reset controller to the PMC where their
 controls really are, adds bindings for the external memory controller
 and video capture controller on Tegra210, as well as CPU frequency
 scaling on Tegra20 and Tegra30.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl6+oyATHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoQEBEACKzY70taxOuZRNhlA+/daMDtiSGijV
 0dXXTXLmFVxXv742UqQsIXdGwiw7Dg/Gm+3B2j+wgQQbVNCvhUGIjlDXydnKhamd
 kkJENp4qqzICfO8PX/Nm2PsKTjKpAzDd3SUTEZS4c8EmeF2hnvycK6t1a/H4pAjw
 RwrREIw8q+iv42+mvGIJfLPrrn66jevboSLUXP5EkkXey6rRP+BMh1UrGobX60b6
 fLiAx+EHd/Pl9X8QLvHwN3RCk7uuTDfx8VeKToOz+3v82JO2eBnU94GLWsSLcHgo
 vSJestoBwDQlUyzpTdFWmm9E0ndwd2OSfbueM+/2Sy1L2CEcxOrNJegmGtE79FKx
 zmogIkW4TNshHBajgXcSkJdwHrcKK9znnKCWJylCWQojtz2oQtXoNL54yTsJGu2F
 /J1hHZWrgdb5SGb7rOJaf1xe7lqzsygJ442tz+Bd3D3U+tW6I8Qz8ZZIxFg4Riog
 4X7gnKN/FrYHJlokD/mPp+S+zeu1z5/q00bk9T2MkvOi+58AZEL0qxbQygPt4JKU
 hCHm4aUf6IYmuczD54DM4EWzurZcFNQdbH5q6VJgNjBUahoUdRkeeURJmV4kK9DM
 TxY2y6oy1WzkdDIMdw/Oj4FmUhUYaswhzZPJkeXFWJu/VPn15gXcmuNylRSQYGkH
 HKjoGRPBgy4lsA==
 =sMK0
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-5.8-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.8-rc1

This adds bindings for the CSI TPG clock on Tegra210, moves various
clocks from the clock and reset controller to the PMC where their
controls really are, adds bindings for the external memory controller
and video capture controller on Tegra210, as well as CPU frequency
scaling on Tegra20 and Tegra30.

* tag 'tegra-for-5.8-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: i2c: tegra: Document Tegra210 VI I2C
  dt-bindings: tegra: Add VI and CSI bindings
  dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
  dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
  dt-bindings: clock: tegra: Remove PMC clock IDs
  dt-bindings: clock: tegra: Add clock ID for CSI TPG clock

Link: https://lore.kernel.org/r/20200515145311.1580134-4-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21 22:30:18 +02:00
Arnd Bergmann
de12d92147 Renesas ARM DT updates for v5.8 (take two)
- Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
     Qseven SOM (G21M) and board (G21D),
   - Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
     Silicon Linux EK874 RZ/G2E evaluation kit.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCXr5g8QAKCRCKwlD9ZEnx
 cDusAQD4SCmyY0MZZNWQhkhu2ics2wYpKItw4Y7E4fl9XUlXkQEAyyN11vVNoteX
 7KvNX7/9eXpberlcx4H6szPQsOzWzwM=
 =2KDk
 -----END PGP SIGNATURE-----

Merge tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.8 (take two)

  - Initial support for the Renesas RZ/G1H SoC on the iWave RainboW
    Qseven SOM (G21M) and board (G21D),
  - Support for the AISTARVISION MIPI Adapter V2.1 camera board on the
    Silicon Linux EK874 RZ/G2E evaluation kit.

* tag 'renesas-arm-dt-for-v5.8-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: r8a774c0-cat874: Add support for AISTARVISION MIPI Adapter V2.1
  ARM: dts: r8a7742: Add GPIO nodes
  ARM: dts: r8a7742: Add [H]SCIF{A|B} support
  ARM: dts: r8a7742: Add IRQC support
  ARM: dts: r8a7742-iwg21d-q7: Add iWave G21D-Q7 board based on RZ/G1H
  ARM: dts: r8a7742-iwg21m: Add iWave RZ/G1H Qseven SOM
  ARM: dts: r8a7742: Initial SoC device tree
  clk: renesas: Add r8a7742 CPG Core Clock Definitions
  dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros

Link: https://lore.kernel.org/r/20200515100547.14671-3-geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-05-21 16:02:12 +02:00
Peng Fan
8c83a8ff4d clk: imx8mp: use imx8m_clk_hw_composite_core to simplify code
Use imx8m_clk_hw_composite_core to simpliy clks that belong to
core clk slice.

Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20 09:26:48 +08:00
Peng Fan
77f5d2d973 clk: imx8mp: Define gates for pll1/2 fixed dividers
Inspried from
commit e8688fe8df ("clk: imx8mn: Define gates for pll1/2 fixed dividers")

On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-20 09:26:45 +08:00
Martin Blumenstingl
cc9ca02a40 dt-bindings: power: meson-ee-pwrc: add support for the Meson GX SoCs
The power domains on the GX SoCs are very similar to G12A. The only
known differences so far are:
- The GX SoCs do not have the HHI_VPU_MEM_PD_REG2 register (for the
  VPU power-domain)
- The GX SoCs have an additional reset line called "dvin"

Add a new compatible string and adjust the reset line expectations for
these SoCs.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200515204709.1505498-3-martin.blumenstingl@googlemail.com
2020-05-19 16:02:14 -07:00
Martin Blumenstingl
18dfc0bf81 dt-bindings: power: meson-ee-pwrc: add support for Meson8/8b/8m2
The power domains on the 32-bit Meson8/Meson8b/Meson8m2 SoCs are very
similar to what G12A still uses. The (known) differences are:
- Meson8 doesn't use any reset lines at all
- Meson8b and Meson8m2 use the same reset lines, which are different
  from what the 64-bit SoCs use
- there is no "vapb" clock on the older SoCs
- amlogic,ao-sysctrl cannot point to the whole AO sysctrl region but
  only the power management related registers

Add a new compatible string and adjust clock and reset line expectations
for each SoC.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200515204709.1505498-2-martin.blumenstingl@googlemail.com
2020-05-19 16:02:14 -07:00
Dilip Kota
c5d3cdad68 dt-bindings: phy: Add PHY_TYPE_XPCS definition
Add definition for Ethernet PCS phy type.

Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-By: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/6091f0d2a1046f1e3656d9e33b6cc433d5465eaf.1589868358.git.eswara.kota@linux.intel.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-05-19 20:26:06 +05:30
Johan Jonker
d09855bdd8 include: dt-bindings: rockchip: remove unused defines
The Rockchip dtsi and dts files have been bulk-converted for the
remaining raw gpio numbers into their descriptive counterparts and
also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
mappings, so remove the unused defines in 'rockchip.h' to prevent
that someone start using them again.

Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20200512203524.7317-3-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2020-05-18 23:39:31 +02:00
Bryan O'Donoghue
4c71d6abc4 clk: qcom: Add DT bindings for MSM8939 GCC
Add compatible strings and the include files for the MSM8939 GCC.

Cc: Andy Gross <agross@kernel.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Tested-by: Vincent Knecht <vincent.knecht@mailoo.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lkml.kernel.org/r/20200512115023.2856617-2-bryan.odonoghue@linaro.org
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14 14:31:33 -07:00
Dong Aisheng
88d93afd77 dt-bindings: firmware: imx: Add more system controls and PM clock types
Add more system controls and PM clock types for usage.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-13 16:19:39 +08:00
Dong Aisheng
755a739794 dt-bindings: firmware: imx: Move system control into dt-binding headfile
i.MX8 SoCs DTS file needs system control macro definitions, so move them
into dt-binding headfile, then include/linux/firmware/imx/types.h can be
removed and those drivers using it should be changed accordingly.

Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-05-13 16:19:23 +08:00
Joseph Lo
cd4d6f3575 clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12 22:48:41 +02:00
Sowjanya Komatineni
796705bcb1 dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock
ID for this CSI TPG clock from PLLD.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12 22:47:14 +02:00
Sowjanya Komatineni
c958540525 dt-bindings: clock: tegra: Remove PMC clock IDs
clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so
these clocks should be provided by the Tegra PMC. IDs for these clocks
have been defined in dt-bindings/soc/tegra-pmc.h.

This patch removes the IDs for these clocks from the Tegra clock device
tree bindings.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12 22:47:14 +02:00
Jerome Brunet
3a5fc2520b dt-bindings: reset: meson: add gxl internal dac reset
Add the reset line of the internal DAC found on the amlogic gxl SoC family

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-05-06 12:03:43 +02:00
Anson Huang
c4e181d6fe dt-bindings: reset: imx7: Document usage on i.MX8MP SoC
The driver now supports i.MX8MP, so update bindings accordingly.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2020-05-06 12:03:43 +02:00